aboutsummaryrefslogtreecommitdiff
path: root/src/northbridge
diff options
context:
space:
mode:
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c13
1 files changed, 0 insertions, 13 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
index ec36c06c16..04a696c2c2 100644
--- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
+++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
@@ -19,7 +19,6 @@
#include <console/console.h>
#include <bootstate.h>
#include <cbmem.h>
-#include <cf9_reset.h>
#include <device/device.h>
#include <southbridge/intel/fsp_rangeley/pci_devs.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
@@ -166,16 +165,4 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
return;
}
-/* The FSP returns here after the fsp_early_init call */
-void ChipsetFspReturnPoint(EFI_STATUS Status,
- VOID *HobListPtr)
-{
- *(void **)CBMEM_FSP_HOB_PTR = HobListPtr;
-
- if (Status == 0xFFFFFFFF) {
- system_reset();
- }
- romstage_main_continue(Status, HobListPtr);
-}
-
#endif /* __PRE_RAM__ */