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-rw-r--r--src/northbridge/amd/amdfam10/amdfam10.h7
-rw-r--r--src/northbridge/amd/amdk8/f.h10
-rw-r--r--src/northbridge/amd/amdk8/pre_f.h6
-rw-r--r--src/northbridge/amd/amdmct/mct/mct_d.h9
-rw-r--r--src/northbridge/intel/common/mrc_cache.h4
-rw-r--r--src/northbridge/intel/haswell/haswell.h3
-rw-r--r--src/northbridge/intel/haswell/pei_data.h8
-rw-r--r--src/northbridge/intel/i82830/smihandler.c11
-rw-r--r--src/northbridge/intel/i945/raminit.h4
-rw-r--r--src/northbridge/intel/nehalem/raminit.c5
-rw-r--r--src/northbridge/intel/sandybridge/pei_data.h4
-rw-r--r--src/northbridge/intel/sandybridge/raminit.h3
-rw-r--r--src/northbridge/intel/sandybridge/raminit_mrc.c3
13 files changed, 48 insertions, 29 deletions
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 611291acbd..e9f714a62e 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -18,6 +18,7 @@
#define AMDFAM10_H
#include <inttypes.h>
+#include <compiler.h>
#include <arch/io.h>
#include <device/device.h>
#include "early_ht.h"
@@ -934,14 +935,14 @@ struct link_pair_t {
u8 nodeid;
u8 linkn;
u8 rsv;
-} __attribute__((packed));
+} __packed;
struct nodes_info_t {
u32 nodes_in_group; // could be 2, 3, 4, 5, 6, 7, 8
u32 groups_in_plane; // could be 1, 2, 3, 4, 5
u32 planes; // could be 1, 2
u32 up_planes; // down planes will be [up_planes, planes)
-} __attribute__((packed));
+} __packed;
struct ht_link_config {
uint32_t ht_speed_limit; // Speed in MHz; 0 for autodetect (default)
@@ -977,7 +978,7 @@ struct sys_info {
struct MCTStatStruc MCTstat;
struct DCTStatStruc DCTstatA[NODE_NUMS];
-} __attribute__((packed));
+} __packed;
/*
diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h
index f3f9c42614..9f09620c95 100644
--- a/src/northbridge/amd/amdk8/f.h
+++ b/src/northbridge/amd/amdk8/f.h
@@ -1,6 +1,8 @@
#ifndef AMDK8_F_H
#define AMDK8_F_H
+#include <compiler.h>
+
/* Definitions of various K8 registers */
/* Function 0 */
#define HT_TRANSACTION_CONTROL 0x68
@@ -465,7 +467,7 @@ struct dimm_size {
uint8_t col;
uint8_t bank; //1, 2, 3 mean 2, 4, 8
uint8_t rank;
-} __attribute__((packed));
+} __packed;
struct mem_info { // pernode
uint32_t dimm_mask;
@@ -483,7 +485,7 @@ struct mem_info { // pernode
uint8_t is_64MuxMode;
uint8_t memclk_set; // we need to use this to retrieve the mem param
uint8_t rsv[2];
-} __attribute__((packed));
+} __packed;
struct link_pair_st {
pci_devfn_t udev;
@@ -493,7 +495,7 @@ struct link_pair_st {
uint32_t pos;
uint32_t offs;
-} __attribute__((packed));
+} __packed;
struct sys_info {
uint8_t ctrl_present[NODE_NUMS];
@@ -516,7 +518,7 @@ struct sys_info {
uint32_t sbdn;
uint32_t sblk;
uint32_t sbbusn;
-} __attribute__((packed));
+} __packed;
#ifdef __PRE_RAM__
#include <arch/early_variables.h>
diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h
index abc51b111f..5b1478bf3c 100644
--- a/src/northbridge/amd/amdk8/pre_f.h
+++ b/src/northbridge/amd/amdk8/pre_f.h
@@ -1,6 +1,8 @@
#ifndef AMDK8_PRE_F_H
#define AMDK8_PRE_F_H
+#include <compiler.h>
+
/* Definitions of various K8 registers */
/* Function 0 */
#define HT_TRANSACTION_CONTROL 0x68
@@ -247,7 +249,7 @@ struct link_pair_st {
uint32_t pos;
uint32_t offs;
-} __attribute__((packed));
+} __packed;
struct sys_info {
uint8_t ctrl_present[NODE_NUMS];
@@ -260,7 +262,7 @@ struct sys_info {
uint32_t sbdn;
uint32_t sblk;
uint32_t sbbusn;
-} __attribute__((packed));
+} __packed;
#ifdef __PRE_RAM__
#include <arch/early_variables.h>
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h
index d13143d979..6a69cfae8c 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct/mct_d.h
@@ -23,6 +23,7 @@
#define DQS_TRAIN_DEBUG 0
#include <inttypes.h>
+#include <compiler.h>
#include "mct_d_gcc.h"
#include <console/console.h>
#include <northbridge/amd/amdfam10/debug.h>
@@ -275,7 +276,7 @@ struct MCTStatStruc {
of sub 4GB dram hole for HW remapping.*/
u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/
u32 SysLimit; /* LIMIT[39:8] (system address)*/
-} __attribute__((packed));
+} __packed;
/*=============================================================================
Global MCT Configuration Status Word (GStatus)
@@ -321,7 +322,7 @@ struct DCTPersistentStatStruc {
/* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/
u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/
u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/
-} __attribute__((packed));
+} __packed;
struct DCTStatStruc { /* A per Node structure*/
@@ -549,7 +550,7 @@ struct DCTStatStruc { /* A per Node structure*/
/* NOTE: This must remain the last entry in this structure */
struct DCTPersistentStatStruc persistentData;
-} __attribute__((packed));
+} __packed;
/*===============================================================================
Local Error Status Codes (DCTStatStruc.ErrCode)
@@ -717,7 +718,7 @@ struct amdmct_memory_info {
struct DCTStatStruc dct_stat[MAX_NODES_SUPPORTED];
uint16_t ecc_enabled;
uint16_t ecc_scrub_rate;
-} __attribute__((packed));
+} __packed;
u32 Get_NB32(u32 dev, u32 reg);
void Set_NB32(u32 dev, u32 reg, u32 val);
diff --git a/src/northbridge/intel/common/mrc_cache.h b/src/northbridge/intel/common/mrc_cache.h
index 1fb6667669..6f0dd6ef74 100644
--- a/src/northbridge/intel/common/mrc_cache.h
+++ b/src/northbridge/intel/common/mrc_cache.h
@@ -1,6 +1,8 @@
#ifndef NORTHBRIDGE_INTEL_COMMON_MRC_CACHE_H
#define NORTHBRIDGE_INTEL_COMMON_MRC_CACHE_H
+#include <compiler.h>
+
#define MRC_DATA_ALIGN 0x1000
#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
@@ -10,7 +12,7 @@ struct mrc_data_container {
u32 mrc_checksum; // IP style checksum
u32 reserved; // For header alignment
u8 mrc_data[0]; // Variable size, platform/run time dependent.
-} __attribute__ ((packed));
+} __packed;
struct mrc_data_container *find_current_mrc_cache(void);
struct mrc_data_container *store_current_mrc_cache(void *data, unsigned length);
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 00616afb49..2d03a68da1 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -186,13 +186,14 @@
#define DMIDRCCFG 0xeb4 /* 32bit */
#ifndef __ASSEMBLER__
+#include <compiler.h>
static inline void barrier(void) { asm("" ::: "memory"); }
struct ied_header {
char signature[10];
u32 size;
u8 reserved[34];
-} __attribute__ ((packed));
+} __packed;
#define PCI_DEVICE_ID_HSW_MOBILE 0x0c04
#define PCI_DEVICE_ID_HSW_ULT 0x0a04
diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h
index f92c0a68e0..f4023e0a6b 100644
--- a/src/northbridge/intel/haswell/pei_data.h
+++ b/src/northbridge/intel/haswell/pei_data.h
@@ -30,6 +30,8 @@
#ifndef PEI_DATA_H
#define PEI_DATA_H
+#include <compiler.h>
+
typedef void (*tx_byte_func)(unsigned char byte);
#define PEI_VERSION 15
@@ -56,12 +58,12 @@ struct usb2_port_setting {
uint8_t enable;
uint8_t over_current_pin;
uint8_t location;
-} __attribute__((packed));
+} __packed;
struct usb3_port_setting {
uint8_t enable;
uint8_t over_current_pin;
-} __attribute__((packed));
+} __packed;
struct pei_data
{
@@ -110,6 +112,6 @@ struct pei_data
struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
uint8_t spd_data[4][256];
tx_byte_func tx_byte;
-} __attribute__((packed));
+} __packed;
#endif
diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c
index 51841e5969..569e62ec7b 100644
--- a/src/northbridge/intel/i82830/smihandler.c
+++ b/src/northbridge/intel/i82830/smihandler.c
@@ -15,6 +15,7 @@
*/
#include <types.h>
+#include <compiler.h>
#include <string.h>
#include <arch/io.h>
#include <console/console.h>
@@ -51,7 +52,7 @@ typedef struct {
u32 function;
u32 retsts;
u32 rfu;
-} __attribute__((packed)) banner_id_t;
+} __packed banner_id_t;
#define MSH_OK 0x0000
#define MSH_OK_RESTART 0x0001
@@ -111,7 +112,7 @@ typedef struct {
u16 versionmajor;
u16 versionminor;
u32 smicombuffersize;
-} __attribute__((packed)) version_t;
+} __packed version_t;
typedef struct {
u16 header_id;
@@ -122,14 +123,14 @@ typedef struct {
u32 type;
u32 header_ext;
u8 name[0];
-} __attribute__((packed)) mbi_header_t;
+} __packed mbi_header_t;
typedef struct {
banner_id_t banner;
u64 handle;
u32 objnum;
mbi_header_t header;
-} __attribute__((packed)) obj_header_t;
+} __packed obj_header_t;
typedef struct {
banner_id_t banner;
@@ -139,7 +140,7 @@ typedef struct {
u32 numbytes;
u32 buflen;
u32 buffer;
-} __attribute__((packed)) get_object_t;
+} __packed get_object_t;
static void mbi_call(u8 subf, banner_id_t *banner_id)
{
diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index bc4491fe2f..4c97d05b7d 100644
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -16,6 +16,8 @@
#ifndef RAMINIT_H
#define RAMINIT_H
+#include <compiler.h>
+
#define DIMM_SOCKETS 2
#define DIMM_TCO_BASE 0x30
@@ -61,7 +63,7 @@ struct sys_info {
u8 banksize[2 * 2 * DIMM_SOCKETS];
const u8 *spd_addresses;
-} __attribute__ ((packed));
+} __packed;
void receive_enable_adjust(struct sys_info *sysinfo);
void sdram_initialize(int boot_path, const u8 *sdram_addresses);
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 122b8ac7cf..b7b445ec86 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -22,6 +22,7 @@
#if REAL
#include <stdlib.h>
+#include <compiler.h>
#include <console/console.h>
#include <string.h>
#include <arch/io.h>
@@ -1906,7 +1907,7 @@ static void send_heci_uma_message(struct raminfo *info)
u8 result;
u8 field2;
u8 unk3[0x48 - 4 - 1];
- } __attribute__ ((packed)) reply;
+ } __packed reply;
struct uma_message {
u8 group_id;
u8 cmd;
@@ -1916,7 +1917,7 @@ static void send_heci_uma_message(struct raminfo *info)
u64 heci_uma_addr;
u32 memory_reserved_for_heci_mb;
u16 c3;
- } __attribute__ ((packed)) msg = {
+ } __packed msg = {
0, MKHI_SET_UMA, 0, 0,
0x82,
info->heci_uma_addr, info->memory_reserved_for_heci_mb, 0};
diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h
index 136d31046e..41fc33fd9a 100644
--- a/src/northbridge/intel/sandybridge/pei_data.h
+++ b/src/northbridge/intel/sandybridge/pei_data.h
@@ -30,6 +30,8 @@
#ifndef PEI_DATA_H
#define PEI_DATA_H
+#include <compiler.h>
+
typedef struct {
uint16_t mode; // 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto
uint16_t hs_port_switch_mask; // 4 bit mask, 1: switchable, 0: not switchable
@@ -129,6 +131,6 @@ struct pei_data
* 2 Always enable double rate
*/
int ddr_refresh_rate_config;
-} __attribute__((packed));
+} __packed;
#endif
diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h
index 4e684ec409..66a94f48d8 100644
--- a/src/northbridge/intel/sandybridge/raminit.h
+++ b/src/northbridge/intel/sandybridge/raminit.h
@@ -16,6 +16,7 @@
#ifndef RAMINIT_H
#define RAMINIT_H
+#include <compiler.h>
#include "pei_data.h"
struct sys_info {
@@ -23,7 +24,7 @@ struct sys_info {
#define BOOT_PATH_NORMAL 0
#define BOOT_PATH_RESET 1
#define BOOT_PATH_RESUME 2
-} __attribute__ ((packed));
+} __packed;
void sdram_initialize(struct pei_data *pei_data);
void save_mrc_data(struct pei_data *pei_data);
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 3f7d1c64ba..7145841ac2 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <compiler.h>
#include <console/console.h>
#include <console/usb.h>
#include <bootmode.h>
@@ -183,7 +184,7 @@ static void report_memory_config(void)
void sdram_initialize(struct pei_data *pei_data)
{
struct sys_info sysinfo;
- int (*entry) (struct pei_data *pei_data) __attribute__ ((regparm(1)));
+ int (*entry) (struct pei_data *pei_data) __attribute__((regparm(1)));
report_platform_info();
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 07:09:53 +0000