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-rw-r--r--src/northbridge/via/cx700/cx700_early_smbus.c2
-rw-r--r--src/northbridge/via/vx800/examples/romstage.c (renamed from src/northbridge/via/vx800/examples/cache_as_ram_auto.c)4
2 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/via/cx700/cx700_early_smbus.c b/src/northbridge/via/cx700/cx700_early_smbus.c
index 218ae0a7a1..ed79744db4 100644
--- a/src/northbridge/via/cx700/cx700_early_smbus.c
+++ b/src/northbridge/via/cx700/cx700_early_smbus.c
@@ -188,7 +188,7 @@ static unsigned int get_spd_data(const struct mem_controller *ctrl, unsigned int
smbus_wait_until_ready();
/* Fetch the SMBus address of the SPD ROM from
- * the ctrl struct in auto.c in case they are at
+ * the ctrl struct in romstage.c in case they are at
* non-standard positions.
* SMBus Address shifted by 1
*/
diff --git a/src/northbridge/via/vx800/examples/cache_as_ram_auto.c b/src/northbridge/via/vx800/examples/romstage.c
index fa8962b168..c1de3f3dc2 100644
--- a/src/northbridge/via/vx800/examples/cache_as_ram_auto.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -559,13 +559,13 @@ g) Rx73h = 32h
}
#endif
/*
-the following code is copied from src\mainboard\tyan\s2735\cache_as_ram_auto.c
+the following code is copied from src/mainboard/tyan/s2735/romstage.c
Only the code around CLEAR_FIRST_1M_RAM is changed.
I remove all the code around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c"
the CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop at somewhere,
and cpu/x86/car/cache_as_ram_post.c do not cache my $CONFIG_XIP_ROM_BASE+SIZE area.
-So,I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c have some diff withx86-version
+So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c have some diff with x86-version
*/
#if 1
{