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-rw-r--r--src/northbridge/via/cx700/early_serial.c2
-rw-r--r--src/northbridge/via/vx800/early_serial.c2
-rw-r--r--src/northbridge/via/vx800/examples/romstage.c1
-rw-r--r--src/northbridge/via/vx800/pci_rawops.h2
4 files changed, 3 insertions, 4 deletions
diff --git a/src/northbridge/via/cx700/early_serial.c b/src/northbridge/via/cx700/early_serial.c
index cde0b31dc5..ae59295200 100644
--- a/src/northbridge/via/cx700/early_serial.c
+++ b/src/northbridge/via/cx700/early_serial.c
@@ -21,7 +21,7 @@
* Enable the serial devices on the VIA CX700
*/
-#include <arch/romcc_io.h>
+#include <arch/io.h>
static void cx700_writepnpaddr(u8 val)
{
diff --git a/src/northbridge/via/vx800/early_serial.c b/src/northbridge/via/vx800/early_serial.c
index b6f58ac580..b3ebde1433 100644
--- a/src/northbridge/via/vx800/early_serial.c
+++ b/src/northbridge/via/vx800/early_serial.c
@@ -20,7 +20,7 @@
/*
* Enable the serial devices on the VIA
*/
-#include <arch/romcc_io.h>
+#include <arch/io.h>
/* The base address is 0x15c, 0x2e, depending on config bytes */
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index 228cc7e3cd..7c3fb7ae87 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -24,7 +24,6 @@
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "console/console.c"
#include "lib/ramtest.c"
diff --git a/src/northbridge/via/vx800/pci_rawops.h b/src/northbridge/via/vx800/pci_rawops.h
index 8e775607bc..33eebc40ac 100644
--- a/src/northbridge/via/vx800/pci_rawops.h
+++ b/src/northbridge/via/vx800/pci_rawops.h
@@ -22,7 +22,7 @@
#define NORTHBRIDGE_VIA_VX800_PCI_RAWOPS_H
#include <stdint.h>
-#include <arch/romcc_io.h>
+#include <arch/io.h>
struct VIA_PCI_REG_INIT_TABLE {
u8 ChipRevisionStart;