diff options
Diffstat (limited to 'src/northbridge/via/vx900/early_host_bus_ctl.c')
| -rw-r--r-- | src/northbridge/via/vx900/early_host_bus_ctl.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/via/vx900/early_host_bus_ctl.c b/src/northbridge/via/vx900/early_host_bus_ctl.c index 159b2a4273..92bb44dda0 100644 --- a/src/northbridge/via/vx900/early_host_bus_ctl.c +++ b/src/northbridge/via/vx900/early_host_bus_ctl.c @@ -19,32 +19,32 @@ static void vx900_cpu_bus_preram_setup(void) { /* Faster CPU to DRAM Cycle */ - pci_mod_config8(HOST_BUS, 0x50, 0x0f, 0x08); + pci_update_config8(HOST_BUS, 0x50, ~0x0f, 0x08); /* CPU Interface Control - Basic Options */ - pci_mod_config8(HOST_BUS, 0x51, 0, 0x6c); + pci_or_config8(HOST_BUS, 0x51, 0x6c); /*CPU Interface Control - Advanced Options */ pci_write_config8(HOST_BUS, 0x52, 0xc7); /* Enable 8QW burst and 4QW request merging [4] and [2] * and special mode for read cycles bit[3] */ - pci_mod_config8(HOST_BUS, 0x54, 0, (1 << 4) | (1 << 2) | (1 << 3)); + pci_or_config8(HOST_BUS, 0x54, (1 << 4) | (1 << 2) | (1 << 3)); /* High priority upstream requests on V4 bus */ pci_write_config8(HOST_BUS, 0x56, 0x03); /* CPU to DRAM extra 1T access control */ - pci_mod_config8(HOST_BUS, 0x59, 0x00, (1 << 2)); + pci_or_config8(HOST_BUS, 0x59, (1 << 2)); /* Queue reordering */ - pci_mod_config8(HOST_BUS, 0x5f, 0x00, (1 << 6)); + pci_or_config8(HOST_BUS, 0x5f, (1 << 6)); /* Only Write cycle of CPU->GFXCTL will flush the CPU->Memory FIFO */ - pci_mod_config8(HOST_BUS, 0x98, 0x00, 0x60); + pci_or_config8(HOST_BUS, 0x98, 0x60); /* 1T delay for data on CPU bus */ pci_write_config8(HOST_BUS, 0x9e, 0x0e); /* Arbitrate ownership of DRAM controller a few cycles earlier */ - pci_mod_config8(HOST_BUS, 0x9f, 0x00, (1 << 7)); + pci_or_config8(HOST_BUS, 0x9f, (1 << 7)); /* Write retire policy */ pci_write_config8(HOST_BUS, 0x5d, 0xa2); /* Occupancy timer */ pci_write_config8(HOST_BUS, 0x53, 0x44); /* Medium Threshold for Write Retire Policy - 6 requests */ - pci_mod_config8(HOST_BUS, 0x56, 0x00, 0x60); + pci_or_config8(HOST_BUS, 0x56, 0x60); /* Bandwidth timer */ pci_write_config8(HOST_BUS, 0x5e, 0x44); } |