diff options
Diffstat (limited to 'src/northbridge/via/vx800/uma_ram_setting.c')
| -rw-r--r-- | src/northbridge/via/vx800/uma_ram_setting.c | 112 |
1 files changed, 0 insertions, 112 deletions
diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c index bf5909316a..46c2782d1a 100644 --- a/src/northbridge/via/vx800/uma_ram_setting.c +++ b/src/northbridge/via/vx800/uma_ram_setting.c @@ -94,23 +94,16 @@ void SetUMARam(void) //GMINT and GFX relatate //note Bit 3 VGA Enable pci_write_config8(MEMCTRL, 0xa7, 0x8c); - // ByteVal = 0x4c; //GMINT Misc.1 - //pci_write_config8(MEMCTRL, 0xb0, 0x80); - - //pci_write_config8(MEMCTRL, 0xb1, 0xaa); //AGPCINT MISC - //pci_write_config8(MEMCTRL, 0xb2, 0x82); - //ByteVal = 0x8A; //GMINT MISC.2 //disable read pass write pci_write_config8(MEMCTRL, 0xb3, 0x9A); //EPLL Register - //pci_write_config8(MEMCTRL, 0xb4, 0x04); //enable CHA and CHB merge mode pci_write_config8(MEMCTRL, 0xde, 0x06); @@ -133,17 +126,12 @@ void SetUMARam(void) ByteVal = (ByteVal & 0x8f) | (SLD0F3Val << 4); pci_write_config8(MEMCTRL, 0xa1, ByteVal); -// vga_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VGA, 0); - //RxB2 may be for S.L. and RxB1 may be for L. L. // It is different from Spec. ByteVal = SLD1F0Val; pci_write_config8(vga_dev, 0xb2, ByteVal); //set M1 size - //ByteVal = pci_read_config8(MEMCTRL, 0xa3); - //ByteVal = 0x02; - //pci_write_config8(MEMCTRL, 0xa3, ByteVal); PRINT_DEBUG_MEM("UMA setting - 3\n"); @@ -177,7 +165,6 @@ void SetUMARam(void) //enable GFx memory space access control for S.L and mmio ByteVal = pci_read_config8(d0f0_dev, 0xD4); ByteVal |= 0x03; - //ByteVal |= 0x01; pci_write_config8(d0f0_dev, 0xD4, ByteVal); //enable Base VGA 16 Bits Decode @@ -189,15 +176,12 @@ void SetUMARam(void) //set VGA memory selection ByteVal = pci_read_config8(vga_dev, 0xb0); ByteVal &= 0xF8; - //ByteVal |= 0x01; ByteVal |= 0x03; pci_write_config8(vga_dev, 0xb0, ByteVal); //set LL size //enable memory access to SL,MMIO,LL and IO to 3B0~3BB,3C0 ~3DF - //ByteVal = 0x03; - //pci_write_config8(d0f0_dev, 0xc0, ByteVal); //Turn on Graphic chip IO port port access ByteVal = inb(0x03C3); @@ -216,9 +200,6 @@ void SetUMARam(void) ByteVal = inb(0x03CC); ByteVal |= 0x03; outb(ByteVal, 0x03C2); - // ByteVal = inb(0x03C2); - // ByteVal |= 0x01; - // outb(ByteVal,0x03C2); #if 1 //bios porting guide has no this two defination: 3d on 3d4/3d5 and 39 on 3c4/3c5 //set frequence 0x3D5.3d[7:4] @@ -329,101 +310,8 @@ void SetUMARam(void) ByteVal = (ByteVal & 0xE5) | 0x1A; outb(ByteVal, 0x03d5); -#if 0 - u8 table3c43c5[0x70] = { - 0x03, 0x01, 0x0F, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x78, 0x00, 0x00, 0x00, 0xBE, 0x20, 0x7F, - 0x60, 0x7F, 0x08, 0x31, 0xCC, 0x00, 0x01, 0x00, - 0x00, 0x18, 0x10, 0x00, 0x00, 0x00, 0x3D, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x04, 0xF3, 0xFF, 0xFC, - 0xF8, 0x0C, 0x00, 0x00, 0x40, 0x06, 0x11, 0x22, - 0x51, 0x10, 0x00, 0x01, 0x19, 0x0C, 0x00, 0xFF, - 0x38, 0x40, 0x30, 0xFF, 0x70, 0x8C, 0x85, 0x9D, - 0x80, 0x05, 0x54, 0x90, 0x03, 0x30, 0x00, 0x5F, - 0x1F, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, - 0x06, 0xDF, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x40, 0x20, 0x00, 0x20, 0x20, - 0xE0, 0x20, 0xD0, 0x3F, 0x00, 0xE0, 0x00, 0x00 - }; - u8 table3d43d5[0x88] = { - 0x7F, 0x63, 0x63, 0x83, 0x69, 0x19, 0x72, 0xE0, - 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x58, 0x9C, 0x57, 0x90, 0x00, 0x57, 0x73, 0xE3, - 0x57, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x0C, 0x00, 0x11, 0x06, 0x00, 0x20, 0x01, 0x34, - 0xEE, 0x74, 0x01, 0x01, 0x08, 0x84, 0x00, 0x00, - 0x00, 0xF3, 0x40, 0x90, 0x00, 0x00, 0x00, 0x01, - 0x00, 0x12, 0x00, 0x02, 0x00, 0x00, 0x10, 0x00, - 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, - 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x9D, 0x9D, 0x10, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x9D, 0x9D, 0x9D, - 0x9D, 0x9D, 0x9D, 0x9D, 0x00, 0x9D, 0x1D, 0x00, - 0x00, 0x00, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, - 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1D, - }; - - u8 table3c0space[0xc0] = { - 0x11, 0x00, 0x10, 0x01, 0x26, 0x3D, 0xFF, 0x00, - 0x10, 0x3F, 0x00, 0x00, 0x2F, 0x00, 0x22, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x50, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - }; - - //for (i = 0;i < 0xc0;i++) - for (i = 0; i < 0x40; i++) - { - outb(table3c0space[i], 0x03c0 + i); - } - - for (i = 0; i < 0x70; i++) { - outb(i, 0x03c4); - outb(table3c43c5[i], 0x03c5); - } - for (i = 0; i < 0x88; i++) { - outb(i, 0x03d4); - outb(table3d43d5[i], 0x03d5); - } - - outb(0x92, 0x03d4); - outb(0x80, 0x03d5); - - outb(0xa3, 0x03d4); - outb(0x00, 0x03d5); - - outb(0xe8, 0x03d4); - outb(0x40, 0x03d5); -#endif - // 3d4 3d freq // IO Port / Index: 3X5.3D // Scratch Pad Register 4 -// outb(0x39,0x03c4); -// outb(1 << SLD0F3Val ,0x03c5); -// #endif - } |