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path: root/src/northbridge/via/vx800/driving_setting.c
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Diffstat (limited to 'src/northbridge/via/vx800/driving_setting.c')
-rw-r--r--src/northbridge/via/vx800/driving_setting.c10
1 files changed, 1 insertions, 9 deletions
diff --git a/src/northbridge/via/vx800/driving_setting.c b/src/northbridge/via/vx800/driving_setting.c
index 3bdfdf391f..c6a7edda05 100644
--- a/src/northbridge/via/vx800/driving_setting.c
+++ b/src/northbridge/via/vx800/driving_setting.c
@@ -55,7 +55,6 @@ void DRAMDriving(DRAM_SYS_ATTR * DramAttr)
DrivingDCLK(DramAttr);
}
-
/*
ODT Control for DQ/DQS/CKE/SCMD/DCLKO in ChA & ChB
which include driving enable/range and strong/weak selection
@@ -158,7 +157,6 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr)
Data |= 0;
pci_write_config8(MEMCTRL, 0x9e, Data);
-
if (DIMMFREQ_400 == DramAttr->DramFreq)
Data = 0x0;
else if (DIMMFREQ_533 == DramAttr->DramFreq)
@@ -171,7 +169,6 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr)
Data = 0;
pci_write_config8(MEMCTRL, 0x9f, Data);
-
/*channel A ODT select */
if (DramAttr->DimmNumChA > 0) {
Data = pci_read_config8(MEMCTRL, 0xd5);
@@ -190,7 +187,6 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr)
Data |= 0x00; /*if rank number is 1or2, clear bit7 */
pci_write_config8(MEMCTRL, 0xd7, Data);
-
/*channel A */
Data = pci_read_config8(MEMCTRL, 0xd5);
Data &= 0xF3; //bit2,3
@@ -212,12 +208,10 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr)
}
if (!bFound) { /*set default value */
Data =
- ODTLookup_TBL[ODTLookup_Tbl_count -
- 1][1];
+ ODTLookup_TBL[ODTLookup_Tbl_count - 1][1];
}
pci_write_config8(MEMCTRL, 0x9c, Data);
-
//set CHA MD ODT control State Dynamic-on
Data = pci_read_config8(MEMCTRL, 0xD4);
Data &= 0xC9;
@@ -252,7 +246,6 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr)
Data |= 0x00; /*if rank number is 1or2, clear bit7 */
pci_write_config8(MEMCTRL, 0xd7, Data);
-
Data = pci_read_config8(MEMCTRL, 0xd5);
Data &= 0xFC;
if (DramAttr->DimmNumChB == 2) /*2 Dimm, 3or4 Ranks */
@@ -267,7 +260,6 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr)
Data |= 0x08;
pci_write_config8(MEMCTRL, 0xD4, Data);
-
//enable CHB differential DQS input
Data = pci_read_config8(MEMCTRL, 0x9E);
Data |= 0x02;