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Diffstat (limited to 'src/northbridge/via/vx800/dev_init.c')
-rw-r--r--src/northbridge/via/vx800/dev_init.c363
1 files changed, 1 insertions, 362 deletions
diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c
index 7ac5fe1999..1bc779f16a 100644
--- a/src/northbridge/via/vx800/dev_init.c
+++ b/src/northbridge/via/vx800/dev_init.c
@@ -61,10 +61,7 @@ static const u8 DramRegTbl[][3] = {
* R/W DRAM.
*/
- // {0x79, 0x00, 0x8F },
{0x85, 0x00, 0x00},
- // {0x90, 0x87, 0x78 },
- // {0x91, 0x00, 0x46 },
{0x40, 0x00, 0x00},
{0, 0, 0}
@@ -94,9 +91,6 @@ void DRAMRegInitValue(DRAM_SYS_ATTR *DramAttr)
Data |= 0x0; /* CHA + CHC */
pci_write_config8(MEMCTRL, 0x6c, Data);
- // Data = 0xAA;
- // pci_write_config8(MEMCTRL, 0xb1, Data);
-
// set CHB DQSB input delay, or else will meet error which
// is some byte is right but another bit is error.
Data = pci_read_config8(MEMCTRL, 0xff);
@@ -104,9 +98,6 @@ void DRAMRegInitValue(DRAM_SYS_ATTR *DramAttr)
pci_write_config8(MEMCTRL, 0xff, Data);
// enable CHC RXDB[7]
- // Data = pci_read_config8(MEMCTRL, 0xdb);
- // Data = (Data & 0x7F) | 0x80;
- // pci_write_config8(MEMCTRL, 0xdb, Data);
// rx62[2:0], CHA and CHB CL
Data = pci_read_config8(MEMCTRL, 0x62);
@@ -473,7 +464,7 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr)
Twr = (Data & 0xE0) >> 5;
AccessAddr += CHA_DDR2_Twr_table[Twr];
- // AccessAddr = 0x1012D8;
+
DimmRead(AccessAddr); /* Set MRS command. */
PRINT_DEBUG_MEM("Step 18 Address");
PRINT_DEBUG_MEM_HEX32(AccessAddr);
@@ -517,358 +508,6 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr)
}
/*===================================================================
-Function : InitDDR2_CHB()
-Precondition :
-Input :
- DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information
- in MotherBoard
-Output : Void
-Purpose : Initialize DDR2 of CHB by standard sequence
-Reference :
-===================================================================*/
-/*// DLL: Enable Reset
-static const u32 CHB_MRS_DLL_150[2] = { 0x00020200 | (1 << 20), 0x00000800 }; // with 150 ohm (A17 = 1, A9 = 1), (A11 = 1)(cpu address)
-//u32 CHB_MRS_DLL_75[2] = { 0x00020020 | (1 << 20), 0x00000800 }; // with 75 ohm (A17 = 1, A5 = 1), (A11 = 1)(cpu address)
-// CPU(DRAM)
-// { DLL: Enable. A17(BA0)=1 and A3(MA0)=0 }
-// { DLL: reset. A11(MA8)=1 }
-//
-// DDR2 CL = 2 CL = 3 CL = 4 CL = 5 (Burst type = interleave)(WR fine tune in code)
-static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // BL = 4; Use 1X-bandwidth MA table to init DRAM
-
-// MA11 MA10(AP) MA9
-#define CHB_MRS_DDR2_TWR2 (0 << 13) + (0 << 20) + (1 << 12) // Value = 001000h
-#define CHB_MRS_DDR2_TWR3 (0 << 13) + (1 << 20) + (0 << 12) // Value = 100000h
-#define CHB_MRS_DDR2_TWR4 (0 << 13) + (1 << 20) + (1 << 12) // Value = 101000h
-#define CHB_MRS_DDR2_TWR5 (1 << 13) + (0 << 20) + (0 << 12) // Value = 002000h
-#define CHB_MRS_DDR2_TWR6 (1 << 13) + (0 << 20) + (1 << 12) // Value = 003000h
-
-// DDR2 Twr = 2 Twr = 3 Twr = 4 Twr = 5
-static const u32 CHB_DDR2_Twr_table[5] = { CHB_MRS_DDR2_TWR2, CHB_MRS_DDR2_TWR3, CHB_MRS_DDR2_TWR4, CHB_MRS_DDR2_TWR5, CHB_MRS_DDR2_TWR6 };
-
-#define CHB_OCD_Exit_150ohm 0x20200 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 1,MA2 = 0 (DRAM bus address)
-// A17 = 1, A12 = A11 = A10 = 0,A9 = 1 ,A5 = 0 (CPU address)
-#define CHB_OCD_Default_150ohm 0x21E00 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 1,MA2 = 0 (DRAM bus address)
-// A17 = 1, A12 = A11 = A10 = 1,A9 = 1 ,A5 = 0 (CPU address)
-//#define CHB_OCD_Exit_75ohm 0x20020 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 0,MA2 = 1 (DRAM bus address)
-// A17 = 1, A12 = A11 = A10 = 0,A9 = 0 ,A5 = 1 (CPU address)
-//#define CHB_OCD_Default_75ohm 0x21C20 | (1 << 20) // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 0,MA2 = 1 (DRAM bus address)
-// A17 = 1, A12 = A11 = A10 = 1,A9 = 0 ,A5 = 1 (CPU address)
-void InitDDR2CHB(
- DRAM_SYS_ATTR *DramAttr
- )
-
-{
- u8 Data;
- u8 Idx, CL, BL, Twr;
- u32 AccessAddr;
-
- Data = 0x80;
- pci_write_config8(MEMCTRL, 0x54, Data);
-
- // step3.
- //disable bank paging and multi page
- Data = pci_read_config8(MEMCTRL, 0x69);
- Data &= ~0x03;
- pci_write_config8(MEMCTRL, 0x69, Data);
-
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data |= 0x80;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
- //step 4. Initialize CHB begin
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data |= 0x40;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
- //Step 5. NOP command enable
- Data = pci_read_config8(MEMCTRL, 0xd7);
- Data &= 0xC7;
- Data |= 0x08;
- pci_write_config8(MEMCTRL, 0xd7, Data);
-
- //Step 6. issue a nop cycle,RegD3[7] 0 -> 1
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data &= 0x7F;
- pci_write_config8(MEMCTRL, 0xd3, Data);
- Data |= 0x80;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
- // Step 7.
- // A minimum pause of 200u sec will be provided after the NOP.
- // - <<< reduce BOOT UP time >>> -
- // Loop 200us
- for (Idx = 0; Idx < 0x10; Idx++)
- WaitMicroSec(10);
-
- // Step 8.
- // all banks precharge command enable
- Data = pci_read_config8(MEMCTRL, 0xd7);
- Data &= 0xC7;
- Data |= 0x10;
- pci_write_config8(MEMCTRL, 0xd7, Data);
-
- //step 9. issue a precharge all cycle,RegD3[7] 0 -> 1
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data &= 0x7F;
- pci_write_config8(MEMCTRL, 0xd3, Data);
- Data |= 0x80;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
- //step10. EMRS enable
- Data = pci_read_config8(MEMCTRL, 0xd7);
- Data &= 0xC7;
- Data |= 0x18;
- pci_write_config8(MEMCTRL, 0xd7, Data);
-
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data &= 0xC7;
- Data |= 0x08;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
- //step11. EMRS DLL Enable and Disable DQS
- AccessAddr = CHB_MRS_DLL_150[0] >> 3;
- Data =(u8) (AccessAddr & 0xff);
- pci_write_config8(MEMCTRL, 0xd9, Data);
-
- Data = (u8)((AccessAddr & 0xff00) >> 8);
- pci_write_config8(MEMCTRL, 0xda, Data);
-
- Data = pci_read_config8(MEMCTRL, 0xd7);
- Data &= 0xF9;
- Data |= (u8)((AccessAddr & 0x30000) >> 15);
- pci_write_config8(MEMCTRL, 0xd7, Data);
-
- //step12. issue EMRS cycle
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data &= 0x7F;
- pci_write_config8(MEMCTRL, 0xd3, Data);
- Data |= 0x80;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
- //step13. MSR enable
- Data = pci_read_config8(MEMCTRL, 0xd7);
- Data &= 0xC7;
- Data |= 0x18;
- pci_write_config8(MEMCTRL, 0xd7, Data);
-
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data &= 0xC7;
- Data |= 0x00;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
- //step 14. MSR DLL Reset
- AccessAddr = CHB_MRS_DLL_150[1] >> 3;
- Data =(u8) (AccessAddr & 0xff);
- pci_write_config8(MEMCTRL, 0xd9, Data);
-
- Data = (u8)((AccessAddr & 0xff00) >> 8);
- pci_write_config8(MEMCTRL, 0xda, Data);
-
- Data = pci_read_config8(MEMCTRL, 0xd7);
- Data &= 0xF9;
- Data |= (u8)((AccessAddr & 0x30000) >> 15);
- pci_write_config8(MEMCTRL, 0xd7, Data);
-
- //step15. issue MRS cycle
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data &= 0x7F;
- pci_write_config8(MEMCTRL, 0xd3, Data);
- Data |= 0x80;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
- //clear the address
- Data = 0x00;
- pci_write_config8(MEMCTRL, 0xda, Data);
-
- //step16. all banks precharge command enable
- Data = pci_read_config8(MEMCTRL, 0xd7);
- Data &= 0xC7;
- Data |= 0x10;
- pci_write_config8(MEMCTRL, 0xd7, Data);
-
-
- // step17. issue precharge all cycle
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data &= 0x7F;
- pci_write_config8(MEMCTRL, 0xd3, Data);
- Data |= 0x80;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
- //step18. CBR cycle enable
- Data = pci_read_config8(MEMCTRL, 0xd7);
- Data &= 0xC7;
- Data |= 0x20;
- pci_write_config8(MEMCTRL, 0xd7, Data);
-
- //step 19.20.21
- //repeat issue 8 CBR cycle, between each cycle stop 100us
- for (Idx = 0; Idx < 8; Idx++)
- {
- // issue CBR cycle
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data &= 0x7F;
- pci_write_config8(MEMCTRL, 0xd3, Data);
- Data |= 0x80;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
- WaitMicroSec(200);
- }
-
- //step22. MSR enable
- Data = pci_read_config8(MEMCTRL, 0xd7);
- Data &= 0xC7;
- Data |= 0x18;
- pci_write_config8(MEMCTRL, 0xd7, Data);
-
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data &= 0xC7;
- Data |= 0x00;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
-
- //the SDRAM parameters.(Burst Length, CAS# Latency , Write recovery etc.)
- //-------------------------------------------------------------
- //Burst Length : really offset Rx6c[1]
- Data = pci_read_config8(MEMCTRL, 0x6C);
- BL = (Data & 0x02) >> 1;
-
- // CL = really offset RX62[2:0]
- Data = pci_read_config8(MEMCTRL, 0x62);
- CL = Data & 0x03;
-
- AccessAddr = (u32)(CHB_DDR2_MRS_table[CL]);
- if (BL)
- {
- AccessAddr += 8;
- }
-
- //Write recovery : really offset Rx63[7:5]
- Data = pci_read_config8(MEMCTRL, 0x63);
- Twr = (Data & 0xE0) >> 5;
-
- AccessAddr += CHB_DDR2_Twr_table[Twr];
- //MSR Address use addr[20:3]
- AccessAddr >>= 3;
-
- //step 23. MSR command
- Data = (u8)(AccessAddr & 0xFF);
- pci_write_config8(MEMCTRL, 0xD9, Data);
-
- Data = (u8)((AccessAddr & 0xFF00) >> 8);
- pci_write_config8(MEMCTRL, 0xda, Data);
-
- Data = pci_read_config8(MEMCTRL, 0xd7);
- Data &= 0xF9;
- Data |= (u8)(((AccessAddr & 0x30000)>>16) << 1);
- pci_write_config8(MEMCTRL, 0xd7, Data);
-
- //step 24. issue MRS cycle
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data &= 0x7F;
- pci_write_config8(MEMCTRL, 0xd3, Data);
- Data |= 0x80;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
- //step 25. EMRS enable
- Data = pci_read_config8(MEMCTRL, 0xd7);
- Data &= 0xC7;
- Data |= 0x18;
- pci_write_config8(MEMCTRL, 0xd7, Data);
-
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data &= 0xC7;
- Data |= 0x08;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
-
- //step 26. OCD default
- AccessAddr = (CHB_OCD_Default_150ohm) >> 3;
- Data =(u8) (AccessAddr & 0xff);
- pci_write_config8(MEMCTRL, 0xd9, Data);
-
- Data = (u8)((AccessAddr & 0xff00) >> 8);
- pci_write_config8(MEMCTRL, 0xda, Data);
-
- Data = pci_read_config8(MEMCTRL, 0xd7);
- Data &= 0xF9;
- Data |= (u8)((AccessAddr & 0x30000) >> 15);
- pci_write_config8(MEMCTRL, 0xd7, Data);
-
- //step 27. issue EMRS cycle
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data &= 0x7F;
- pci_write_config8(MEMCTRL, 0xd3, Data);
- Data |= 0x80;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
- //step 25. EMRS enable
- Data = pci_read_config8(MEMCTRL, 0xd7);
- Data &= 0xC7;
- Data |= 0x18;
- pci_write_config8(MEMCTRL, 0xd7, Data);
-
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data &= 0xC7;
- Data |= 0x08;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
- //step 28. OCD Exit
- AccessAddr = (CHB_OCD_Exit_150ohm) >> 3;
- Data =(u8) (AccessAddr & 0xff);
- pci_write_config8(MEMCTRL, 0xd9, Data);
-
- Data = (u8)((AccessAddr & 0xff00) >> 8);
- pci_write_config8(MEMCTRL, 0xda, Data);
-
- Data = pci_read_config8(MEMCTRL, 0xd7);
- Data &= 0xF9;
- Data |= (u8)((AccessAddr & 0x30000) >> 15);
- pci_write_config8(MEMCTRL, 0xd7, Data);
-
- //step 29. issue EMRS cycle
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data &= 0x7F;
- pci_write_config8(MEMCTRL, 0xd3, Data);
- Data |= 0x80;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
- //clear all the address
- Data = 0x00;
- pci_write_config8(MEMCTRL, 0xd9, Data);
-
- Data = 0x00;
- pci_write_config8(MEMCTRL, 0xda, Data);
-
- Data = pci_read_config8(MEMCTRL, 0xd7);
- Data &= 0xF9;
- pci_write_config8(MEMCTRL, 0xd7, Data);
-
- //step 30. normal SDRAM Mode
- Data = pci_read_config8(MEMCTRL, 0xd7);
- Data &= 0xC7;
- Data |= 0x00;
- pci_write_config8(MEMCTRL, 0xd7, Data);
-
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data &= 0xC7;
- Data |= 0x00;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
- //step 31. exit the initialization mode
- Data = pci_read_config8(MEMCTRL, 0xd3);
- Data &= 0xBF;
- pci_write_config8(MEMCTRL, 0xd3, Data);
-
-
- //step 32. Enable bank paging and multi page
- Data = pci_read_config8(MEMCTRL, 0x69);
- Data |= 0x03;
- pci_write_config8(MEMCTRL, 0x69, Data);
-}
-*/
-
-/*===================================================================
Function : InitDDR2CHC()
Precondition :
Input :
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-26 13:23:02 +0000