aboutsummaryrefslogtreecommitdiff
path: root/src/northbridge/via/vx800/clk_ctrl.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/northbridge/via/vx800/clk_ctrl.c')
-rw-r--r--src/northbridge/via/vx800/clk_ctrl.c211
1 files changed, 90 insertions, 121 deletions
diff --git a/src/northbridge/via/vx800/clk_ctrl.c b/src/northbridge/via/vx800/clk_ctrl.c
index 13edc1f996..ec070ee1c7 100644
--- a/src/northbridge/via/vx800/clk_ctrl.c
+++ b/src/northbridge/via/vx800/clk_ctrl.c
@@ -17,11 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-void DutyCycleCtrl(DRAM_SYS_ATTR * DramAttr)
+void DutyCycleCtrl(DRAM_SYS_ATTR *DramAttr)
{
- u8 Data;
- u8 FreqId;
- u8 i;
+ u8 Data, FreqId, i;
if (DIMMFREQ_800 == DramAttr->DramFreq)
FreqId = 2;
@@ -34,64 +32,54 @@ void DutyCycleCtrl(DRAM_SYS_ATTR * DramAttr)
else
FreqId = 5;
- if (DramAttr->RankNumChA > 0) { // 1 rank
+ if (DramAttr->RankNumChA > 0) { /* 1 rank */
for (i = 0; i < DUTY_CYCLE_REG_NUM; i++) {
- Data =
- pci_read_config8(MEMCTRL,
- ChA_Duty_Control_DDR2[i][0]);
- Data &= ChA_Duty_Control_DDR2[i][1]; /*Mask */
- Data |= ChA_Duty_Control_DDR2[i][FreqId]; /*set Value */
+ Data = pci_read_config8(MEMCTRL,
+ ChA_Duty_Control_DDR2[i][0]);
+ Data &= ChA_Duty_Control_DDR2[i][1]; /* mask */
+ Data |= ChA_Duty_Control_DDR2[i][FreqId]; /* set val */
pci_write_config8(MEMCTRL,
- ChA_Duty_Control_DDR2[i][0],
- Data);
+ ChA_Duty_Control_DDR2[i][0], Data);
}
}
- if (1 == ENABLE_CHC) { // 1 rank
+
+ if (1 == ENABLE_CHC) { /* 1 rank */
for (i = 0; i < DUTY_CYCLE_REG_NUM; i++) {
- Data =
- pci_read_config8(MEMCTRL,
- ChB_Duty_Control_DDR2[i][0]);
- Data &= ChB_Duty_Control_DDR2[i][1]; /*Mask */
- Data |= ChB_Duty_Control_DDR2[i][FreqId]; /*set Value */
+ Data = pci_read_config8(MEMCTRL,
+ ChB_Duty_Control_DDR2[i][0]);
+ Data &= ChB_Duty_Control_DDR2[i][1]; /* mask */
+ Data |= ChB_Duty_Control_DDR2[i][FreqId]; /* set val */
pci_write_config8(MEMCTRL,
- ChB_Duty_Control_DDR2[i][0],
- Data);
+ ChB_Duty_Control_DDR2[i][0], Data);
}
}
-
}
/*
-DRAM clock phase and delay control
-*/
-//sub routine list
-void ClkPhsCtrlFBMDDR2(DRAM_SYS_ATTR * DramAttr);
-
-void WrtDataPhsCtrl(DRAM_SYS_ATTR * DramAttr);
-
-void DQDQSOutputDlyCtrl(DRAM_SYS_ATTR * DramAttr);
-
-void DQSInputCaptureCtrl(DRAM_SYS_ATTR * DramAttr);
-
-void DCLKPhsCtrl(DRAM_SYS_ATTR * DramAttr);
+ * DRAM clock phase and delay control
+ */
+/* Subroutine list */
+void ClkPhsCtrlFBMDDR2(DRAM_SYS_ATTR *DramAttr);
+void WrtDataPhsCtrl(DRAM_SYS_ATTR *DramAttr);
+void DQDQSOutputDlyCtrl(DRAM_SYS_ATTR *DramAttr);
+void DQSInputCaptureCtrl(DRAM_SYS_ATTR *DramAttr);
+void DCLKPhsCtrl(DRAM_SYS_ATTR *DramAttr);
-void DRAMClkCtrl(DRAM_SYS_ATTR * DramAttr)
+void DRAMClkCtrl(DRAM_SYS_ATTR *DramAttr)
{
- /*write data clock phase control */
+ /* Write data clock phase control. */
WrtDataPhsCtrl(DramAttr);
- /*clock phase control */
+ /* Clock phase control */
ClkPhsCtrlFBMDDR2(DramAttr);
/**/ DQDQSOutputDlyCtrl(DramAttr);
/**/ DQSInputCaptureCtrl(DramAttr);
DCLKPhsCtrl(DramAttr);
}
-void ClkPhsCtrlFBMDDR2(DRAM_SYS_ATTR * DramAttr)
+void ClkPhsCtrlFBMDDR2(DRAM_SYS_ATTR *DramAttr)
{
- u8 Data;
-
- u8 FreqId, i;
+ u8 Data, FreqId, i;
if (DramAttr->DramFreq == DIMMFREQ_800)
FreqId = 2;
@@ -103,54 +91,45 @@ void ClkPhsCtrlFBMDDR2(DRAM_SYS_ATTR * DramAttr)
FreqId = 5;
else
FreqId = 5;
- /*channel A */// 2~4 Rank
- if (DramAttr->RankNumChA == 1) { // 1 rank
+
+ /* Channel A */
+ // 2~4 Rank
+ if (DramAttr->RankNumChA == 1) { /* 1 rank */
for (i = 0; i < 3; i++) {
- Data =
- pci_read_config8(MEMCTRL,
- DDR2_ChA_Clk_Phase_Table_1R[i]
- [0]);
- Data &= DDR2_ChA_Clk_Phase_Table_1R[i][1]; /*Mask */
- Data |= DDR2_ChA_Clk_Phase_Table_1R[i][FreqId]; /*set Value */
+ Data = pci_read_config8(MEMCTRL,
+ DDR2_ChA_Clk_Phase_Table_1R[i][0]);
+ Data &= DDR2_ChA_Clk_Phase_Table_1R[i][1]; /* mask */
+ Data |= DDR2_ChA_Clk_Phase_Table_1R[i][FreqId]; /* set val */
pci_write_config8(MEMCTRL,
- DDR2_ChA_Clk_Phase_Table_1R[i]
- [0], Data);
+ DDR2_ChA_Clk_Phase_Table_1R[i][0], Data);
}
- } else if (DramAttr->RankNumChA > 1) { // 2~4 Rank
+ } else if (DramAttr->RankNumChA > 1) { /* 2~4 Rank */
for (i = 0; i < 3; i++) {
- Data =
- pci_read_config8(MEMCTRL,
- DDR2_ChA_Clk_Phase_Table_2R[i]
- [0]);
- Data &= DDR2_ChA_Clk_Phase_Table_2R[i][1]; /*Mask */
- Data |= DDR2_ChA_Clk_Phase_Table_2R[i][FreqId]; /*set Value */
+ Data = pci_read_config8(MEMCTRL,
+ DDR2_ChA_Clk_Phase_Table_2R[i][0]);
+ Data &= DDR2_ChA_Clk_Phase_Table_2R[i][1]; /* mask */
+ Data |= DDR2_ChA_Clk_Phase_Table_2R[i][FreqId]; /* set val */
pci_write_config8(MEMCTRL,
- DDR2_ChA_Clk_Phase_Table_2R[i]
- [0], Data);
+ DDR2_ChA_Clk_Phase_Table_2R[i][0], Data);
}
}
#if ENABLE_CHB
- if (DramAttr->RankNumChB > 0) { // 1 rank
+ if (DramAttr->RankNumChB > 0) { /* 1 rank */
for (i = 0; i < 3; i++) {
- Data =
- pci_read_config8(MEMCTRL,
- DDR2_ChB_Clk_Phase_Table_1R[i]
- [0]);
- Data &= DDR2_ChB_Clk_Phase_Table_1R[i][1]; /*Mask */
- Data |= DDR2_ChB_Clk_Phase_Table_1R[i][FreqId]; /*set Value */
+ Data = pci_read_config8(MEMCTRL,
+ DDR2_ChB_Clk_Phase_Table_1R[i][0]);
+ Data &= DDR2_ChB_Clk_Phase_Table_1R[i][1]; /* mask */
+ Data |= DDR2_ChB_Clk_Phase_Table_1R[i][FreqId]; /* set val */
pci_write_config8(MEMCTRL,
- DDR2_ChB_Clk_Phase_Table_1R[i]
- [0], Data);
+ DDR2_ChB_Clk_Phase_Table_1R[i][0], Data);
}
}
#endif
}
-void WrtDataPhsCtrl(DRAM_SYS_ATTR * DramAttr)
+void WrtDataPhsCtrl(DRAM_SYS_ATTR *DramAttr)
{
- u8 Data;
- u8 FreqId, i;
-
+ u8 Data, FreqId, i;
if (DIMMFREQ_800 == DramAttr->DramFreq)
FreqId = 2;
@@ -163,31 +142,25 @@ void WrtDataPhsCtrl(DRAM_SYS_ATTR * DramAttr)
else
FreqId = 5;
- if (DramAttr->RankNumChA > 0) { // 1 rank
+ if (DramAttr->RankNumChA > 0) { /* 1 rank */
for (i = 0; i < WrtData_REG_NUM; i++) {
- Data =
- pci_read_config8(MEMCTRL,
- DDR2_ChA_WrtData_Phase_Table
- [i][0]);
- Data &= DDR2_ChA_WrtData_Phase_Table[i][1]; /*Mask */
- Data |= DDR2_ChA_WrtData_Phase_Table[i][FreqId]; /*set Value */
+ Data = pci_read_config8(MEMCTRL,
+ DDR2_ChA_WrtData_Phase_Table[i][0]);
+ Data &= DDR2_ChA_WrtData_Phase_Table[i][1]; /* mask */
+ Data |= DDR2_ChA_WrtData_Phase_Table[i][FreqId]; /* set val */
pci_write_config8(MEMCTRL,
- DDR2_ChA_WrtData_Phase_Table[i]
- [0], Data);
+ DDR2_ChA_WrtData_Phase_Table[i][0], Data);
}
}
#if ENABLE_CHB
- if (DramAttr->RankNumChB > 0) { // 1 rank
+ if (DramAttr->RankNumChB > 0) { /* 1 rank */
for (i = 0; i < WrtData_REG_NUM; i++) {
- Data =
- pci_read_config8(MEMCTRL,
- DDR2_ChB_WrtData_Phase_Table
- [i][0]);
- Data &= DDR2_ChB_WrtData_Phase_Table[i][1]; /*Mask */
- Data |= DDR2_ChB_WrtData_Phase_Table[i][FreqId]; /*set Value */
+ Data = pci_read_config8(MEMCTRL,
+ DDR2_ChB_WrtData_Phase_Table[i][0]);
+ Data &= DDR2_ChB_WrtData_Phase_Table[i][1]; /* mask */
+ Data |= DDR2_ChB_WrtData_Phase_Table[i][FreqId]; /* set val */
pci_write_config8(MEMCTRL,
- DDR2_ChB_WrtData_Phase_Table[i]
- [0], Data);
+ DDR2_ChB_WrtData_Phase_Table[i][0], Data);
}
}
#endif
@@ -197,10 +170,9 @@ void WrtDataPhsCtrl(DRAM_SYS_ATTR * DramAttr)
pci_write_config8(MEMCTRL, 0x8C, Data);
}
-void DQDQSOutputDlyCtrl(DRAM_SYS_ATTR * DramAttr)
+void DQDQSOutputDlyCtrl(DRAM_SYS_ATTR *DramAttr)
{
- u8 Data;
- u8 FreqId;
+ u8 Data, FreqId;
if (DIMMFREQ_400 == DramAttr->DramFreq)
FreqId = 0;
@@ -212,6 +184,7 @@ void DQDQSOutputDlyCtrl(DRAM_SYS_ATTR * DramAttr)
FreqId = 2;
else
FreqId = 0;
+
if (DramAttr->RankNumChA > 0) {
Data = DDR2_CHA_DQ_DQS_Delay_Table[FreqId][0];
pci_write_config8(MEMCTRL, 0xf0, Data);
@@ -242,10 +215,9 @@ void DQDQSOutputDlyCtrl(DRAM_SYS_ATTR * DramAttr)
#endif
}
-void DQSInputCaptureCtrl(DRAM_SYS_ATTR * DramAttr)
+void DQSInputCaptureCtrl(DRAM_SYS_ATTR *DramAttr)
{
- u8 Data;
- u8 FreqId, i;
+ u8 Data, FreqId, i;
if (DIMMFREQ_800 == DramAttr->DramFreq)
FreqId = 2;
@@ -261,52 +233,49 @@ void DQSInputCaptureCtrl(DRAM_SYS_ATTR * DramAttr)
Data = 0x8A;
pci_write_config8(MEMCTRL, 0x77, Data);
- if (DramAttr->RankNumChA > 0) { // 1 rank
+ if (DramAttr->RankNumChA > 0) { /* 1 rank */
for (i = 0; i < DQS_INPUT_CAPTURE_REG_NUM; i++) {
- Data =
- pci_read_config8(MEMCTRL,
- DDR2_ChA_DQS_Input_Capture_Tbl
- [i][0]);
- Data &= DDR2_ChA_DQS_Input_Capture_Tbl[i][1]; /*Mask */
- Data |= DDR2_ChA_DQS_Input_Capture_Tbl[i][FreqId]; /*set Value */
+ Data = pci_read_config8(MEMCTRL,
+ DDR2_ChA_DQS_Input_Capture_Tbl[i][0]);
+ Data &= DDR2_ChA_DQS_Input_Capture_Tbl[i][1]; /* mask */
+ Data |= DDR2_ChA_DQS_Input_Capture_Tbl[i][FreqId]; /* set val */
pci_write_config8(MEMCTRL,
- DDR2_ChA_DQS_Input_Capture_Tbl[i]
- [0], Data);
+ DDR2_ChA_DQS_Input_Capture_Tbl[i][0], Data);
}
}
#if ENABLE_CHB
- if (DramAttr->RankNumChB > 0) { // 1 rank
+ if (DramAttr->RankNumChB > 0) { /* 1 rank */
for (i = 0; i < DQS_INPUT_CAPTURE_REG_NUM; i++) {
- Data =
- pci_read_config8(MEMCTRL,
- DDR2_ChB_DQS_Input_Capture_Tbl
- [i][0]);
- Data &= DDR2_ChB_DQS_Input_Capture_Tbl[i][1]; /*Mask */
- Data |= DDR2_ChB_DQS_Input_Capture_Tbl[i][FreqId]; /*set Value */
+ Data = pci_read_config8(MEMCTRL,
+ DDR2_ChB_DQS_Input_Capture_Tbl[i][0]);
+ Data &= DDR2_ChB_DQS_Input_Capture_Tbl[i][1]; /* mask */
+ Data |= DDR2_ChB_DQS_Input_Capture_Tbl[i][FreqId]; /* set val */
pci_write_config8(MEMCTRL,
- DDR2_ChB_DQS_Input_Capture_Tbl[i]
- [0], Data);
+ DDR2_ChB_DQS_Input_Capture_Tbl[i][0], Data);
}
}
#endif
}
-//This is very important, if you don't set it correctly, dram will be unreliable
-//set DCLK Phase control(Reg99H[6:1]) according the DDRII in the dimm
-void DCLKPhsCtrl(DRAM_SYS_ATTR * DramAttr)
+/*
+ * This is very important, if you don't set it correctly, DRAM will be
+ * unreliable,
+ *
+ * Set DCLK Phase control(Reg99H[6:1]) according the DDRII in the DIMM.
+ */
+void DCLKPhsCtrl(DRAM_SYS_ATTR *DramAttr)
{
u8 Data;
- Data = 0;
+ Data = 0; /* TODO: Can be dropped? */
Data = pci_read_config8(MEMCTRL, 0x99);
Data &= 0xE1;
- //DDR in Dimm1, MCLKOA[4,3,0] will output MCLK
+ /* DDR in Dimm1, MCLKOA[4,3,0] will output MCLK */
if (DramAttr->RankPresentMap & 0x03)
Data |= 0x09 << 1;
- //DDR in Dimm2, MCLKOA[5,2,1] will output MCLK
+ /* DDR in Dimm2, MCLKOA[5,2,1] will output MCLK */
if (DramAttr->RankPresentMap & 0x0C)
Data |= 0x06 << 1;
pci_write_config8(MEMCTRL, 0x99, Data);
-
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-24 15:58:26 +0000