diff options
Diffstat (limited to 'src/northbridge/via/cx700/raminit.c')
| -rw-r--r-- | src/northbridge/via/cx700/raminit.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index 7d3fcbeb0b..14a17d4771 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -90,7 +90,7 @@ #define REGISTERPRESET(bus,dev,fun,bdfspec) \ { u8 j, reg; \ - for (j=0; j<(sizeof((bdfspec))/sizeof(struct regmask)); j++) { \ + for (j = 0; j < (sizeof((bdfspec))/sizeof(struct regmask)); j++) { \ printk(BIOS_DEBUG, "Writing bus " #bus " dev " #dev " fun " #fun " register "); \ printk(BIOS_DEBUG, "%02x", (bdfspec)[j].reg); \ printk(BIOS_DEBUG, "\n"); \ @@ -303,8 +303,8 @@ static const u8 Init_Rank_Reg_Table[] = { static const u16 DDR2_MRS_table[] = { /* CL: 2, 3, 4, 5 */ - 0x150, 0x1d0, 0x250, 0x2d0, /* BL=4 ;Use 1X-bandwidth MA table to init DRAM */ - 0x158, 0x1d8, 0x258, 0x2d8, /* BL=8 ;Use 1X-bandwidth MA table to init DRAM */ + 0x150, 0x1d0, 0x250, 0x2d0, /* BL = 4 ;Use 1X-bandwidth MA table to init DRAM */ + 0x158, 0x1d8, 0x258, 0x2d8, /* BL = 8 ;Use 1X-bandwidth MA table to init DRAM */ }; #define MRS_DDR2_TWR2 ((0 << 15) | (0 << 20) | (1 << 12)) @@ -1050,7 +1050,7 @@ static void step_2_19(const struct mem_controller *ctrl) /* Step 17. Mode register set. Wait 200us. */ printk(BIOS_SPEW, "\nRAM Enable 4: Mode register set\n"); - //safe value for now, BL=8, WR=4, CAS=4 + //safe value for now, BL = 8, WR = 4, CAS = 4 do_ram_command(ctrl, RAM_COMMAND_MRS); udelay(200); |