1 files changed, 117 insertions, 114 deletions

diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index 20efdea8cd..715305268e 100644
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -25,7 +25,7 @@
 #include <delay.h>
 #include "cn700.h"
 
-//#define DEBUG_RAM_SETUP 1
+// #define DEBUG_RAM_SETUP 1
 
 #ifdef DEBUG_RAM_SETUP
 #define PRINT_DEBUG_MEM(x)		print_debug(x)
@@ -60,16 +60,16 @@ static void do_ram_command(device_t dev, u8 command)
 }
 
 /**
- * Configure the bus between the cpu and the northbridge. This might be able to 
+ * Configure the bus between the CPU and the northbridge. This might be able to 
  * be moved to post-ram code in the future. For the most part, these registers
  * should not be messed around with. These are too complex to explain short of
  * copying the datasheets into the comments, but most of these values are from
  * the BIOS Porting Guide, so they should work on any board. If they don't,
  * try the values from your factory BIOS.
  *
- * TODO: Changing the DRAM frequency doesn't work (hard lockup)
+ * TODO: Changing the DRAM frequency doesn't work (hard lockup).
  *
- * @param dev The northbridge's CPU Host Interface (D0F2)
+ * @param dev The northbridge's CPU Host Interface (D0F2).
  */
 static void c7_cpu_setup(device_t dev)
 {
@@ -87,13 +87,15 @@ static void c7_cpu_setup(device_t dev)
 	/* Write Policy */
 	pci_write_config8(dev, 0x56, 0x01);
 	/* Miscellaneous Control */
-	/* DRAM Operating Frequency (Bits 7:5)
-	 *	000 : 100MHz	001 : 133MHz
-	 *	010 : 166MHz	011 : 200MHz
-	 *	100 : 266MHz	101 : 333MHz
-	 *	110/111 : Reserved */
+	/*
+	 * DRAM Operating Frequency (bits 7:5)
+	 *      000 : 100MHz    001 : 133MHz
+	 *      010 : 166MHz    011 : 200MHz
+	 *      100 : 266MHz    101 : 333MHz
+	 *      110/111 : Reserved
+	 */
 	/* CPU Miscellaneous Control */
-	pci_write_config8(dev, 0x59, 0x44);	
+	pci_write_config8(dev, 0x59, 0x44);
 	/* Write Policy */
 	pci_write_config8(dev, 0x5d, 0xb2);
 	/* Bandwidth Timer */
@@ -112,8 +114,8 @@ static void c7_cpu_setup(device_t dev)
 	/* Read Line Burst DRDY# Timing Control */
 	pci_write_config8(dev, 0x66, 0xff);
 	pci_write_config8(dev, 0x67, 0x30);
-		
-	/* Host Bus IO Circuit (See datasheet) */
+
+	/* Host Bus I/O Circuit (see datasheet) */
 	/* Host Address Pullup/down Driving */
 	pci_write_config8(dev, 0x70, 0x11);
 	pci_write_config8(dev, 0x71, 0x11);
@@ -133,7 +135,7 @@ static void c7_cpu_setup(device_t dev)
 	pci_write_config8(dev, 0x79, 0xaa);
 	/* Address Strobe Input Delay Control */
 	pci_write_config8(dev, 0x7a, 0x24);
-	// Address CKG Rising/Falling Time Control
+	/* Address CKG Rising/Falling Time Control */
 	pci_write_config8(dev, 0x7b, 0xaa);
 	/* Address CKG Clock Rising/Falling Time Control */
 	pci_write_config8(dev, 0x7c, 0x00);
@@ -148,10 +150,10 @@ static void c7_cpu_setup(device_t dev)
 }
 
 /**
- * Set up dram size according to spd data. Eventually, DRAM timings should be 
+ * Set up DRAM size according to SPD data. Eventually, DRAM timings should be
  * done in a similar manner.
  *
- * @param ctrl The northbridge devices and spd addresses.
+ * @param ctrl The northbridge devices and SPD addresses.
  */
 static void sdram_set_size(const struct mem_controller *ctrl)
 {
@@ -159,37 +161,37 @@ static void sdram_set_size(const struct mem_controller *ctrl)
 
 	ranks = spd_read_byte(ctrl->channel0[0], SPD_NUM_DIMM_BANKS);
 	ranks = (ranks & 0x07) + 1;
-	density = spd_read_byte(ctrl->channel0[0], SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
-	switch (density)
-	{
-		case 0x80:
-			result = 0x08;	/* 512MB / 64MB = 0x08 */
-			break;
-		case 0x40:
-			result = 0x04;
-			break;
-		case 0x20:
-			result = 0x02;
-			break;
-		case 0x10:
-			result = 0xff;	/* 16GB */
-			break;
-		case 0x08:
-			result = 0xff;	/* 8GB */
-			break;
-		case 0x04:
-			result = 0xff;	/* 4GB */
-			break;
-		case 0x02:
-			result = 0x20;	/* 2GB */
-			break;
-		case 0x01:
-			result = 0x10;	/* 1GB */
-			break;
+	density = spd_read_byte(ctrl->channel0[0],
+				SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
+	switch (density) {
+	case 0x80:
+		result = 0x08;	/* 512MB / 64MB = 0x08 */
+		break;
+	case 0x40:
+		result = 0x04;
+		break;
+	case 0x20:
+		result = 0x02;
+		break;
+	case 0x10:
+		result = 0xff;	/* 16GB */
+		break;
+	case 0x08:
+		result = 0xff;	/* 8GB */
+		break;
+	case 0x04:
+		result = 0xff;	/* 4GB */
+		break;
+	case 0x02:
+		result = 0x20;	/* 2GB */
+		break;
+	case 0x01:
+		result = 0x10;	/* 1GB */
+		break;
 	}
 
 	if (result == 0xff)
-		die("dram module size too big, not supported by cn700\r\n");
+		die("DRAM module size too big, not supported by CN700\r\n");
 
 	pci_write_config8(ctrl->d0f3, 0x40, result);
 	pci_write_config8(ctrl->d0f3, 0x48, 0x00);
@@ -197,7 +199,7 @@ static void sdram_set_size(const struct mem_controller *ctrl)
 		pci_write_config8(ctrl->d0f3, 0x41, result * ranks);
 		pci_write_config8(ctrl->d0f3, 0x49, result);
 	}
-	/* size mirror */
+	/* Size mirror */
 	pci_write_config8(ctrl->d0f7, 0xe5, (result * ranks) << 2);
 	pci_write_config8(ctrl->d0f7, 0x57, (result * ranks) << 2);
 	/* Low Top Address */
@@ -207,55 +209,53 @@ static void sdram_set_size(const struct mem_controller *ctrl)
 
 	/* Physical-Virtual Mapping */
 	if (ranks == 2)
-		pci_write_config8(ctrl->d0f3, 0x54, 1 << 7 | 0 << 4 | 1 << 3 | 1 << 0);
+		pci_write_config8(ctrl->d0f3, 0x54,
+				  1 << 7 | 0 << 4 | 1 << 3 | 1 << 0);
 	if (ranks == 1)
 		pci_write_config8(ctrl->d0f3, 0x54, 1 << 7 | 0 << 4);
 	pci_write_config8(ctrl->d0f3, 0x55, 0x00);
-	/* virtual rank interleave, disable */
+	/* Virtual rank interleave, disable */
 	pci_write_config32(ctrl->d0f3, 0x58, 0x00);
 
 	/* MA Map Type */
 	result = spd_read_byte(ctrl->channel0[0], SPD_NUM_BANKS_PER_SDRAM);
 	if (result == 8) {
 		col = spd_read_byte(ctrl->channel0[0], SPD_NUM_COLUMNS);
-		switch (col)
-		{
-			case 10:
-				pci_write_config8(ctrl->d0f3, 0x50, 0xa0);
-				break;
-			case 11:
-				pci_write_config8(ctrl->d0f3, 0x50, 0xc0);
-				break;
-			case 12:
-				pci_write_config8(ctrl->d0f3, 0x50, 0xe0);
-				break;
+		switch (col) {
+		case 10:
+			pci_write_config8(ctrl->d0f3, 0x50, 0xa0);
+			break;
+		case 11:
+			pci_write_config8(ctrl->d0f3, 0x50, 0xc0);
+			break;
+		case 12:
+			pci_write_config8(ctrl->d0f3, 0x50, 0xe0);
+			break;
 		}
-	}
-	else if (result == 4) {
+	} else if (result == 4) {
 		col = spd_read_byte(ctrl->channel0[0], SPD_NUM_COLUMNS);
-		switch (col)
-		{
-			case 9:
-				pci_write_config8(ctrl->d0f3, 0x50, 0x00);
-				break;
-			case 10:
-				pci_write_config8(ctrl->d0f3, 0x50, 0x20);
-				break;
-			case 11:
-				pci_write_config8(ctrl->d0f3, 0x50, 0x40);
-				break;
-			case 12:
-				pci_write_config8(ctrl->d0f3, 0x50, 0x60);
-				break;
+		switch (col) {
+		case 9:
+			pci_write_config8(ctrl->d0f3, 0x50, 0x00);
+			break;
+		case 10:
+			pci_write_config8(ctrl->d0f3, 0x50, 0x20);
+			break;
+		case 11:
+			pci_write_config8(ctrl->d0f3, 0x50, 0x40);
+			break;
+		case 12:
+			pci_write_config8(ctrl->d0f3, 0x50, 0x60);
+			break;
 		}
 	}
 	pci_write_config8(ctrl->d0f3, 0x51, 0x00);
 }
 
 /**
- * Set up various ram and other control registers statically. Some of these may 
- * not be needed, other should be done with spd info, but that's a project for
- * the future
+ * Set up various RAM and other control registers statically. Some of these may 
+ * not be needed, other should be done with SPD info, but that's a project for
+ * the future.
  */
 static void sdram_set_registers(const struct mem_controller *ctrl)
 {
@@ -265,48 +265,49 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 	pci_write_config8(ctrl->d0f3, 0x61, 0xe0);
 	/* Set CAS=4 */
 	pci_write_config8(ctrl->d0f3, 0x62, 0xfa);
-	/* dram timing-3 */
+	/* DRAM timing-3 */
 	pci_write_config8(ctrl->d0f3, 0x63, 0xca);
-	/* dram timing-4 */
+	/* DRAM timing-4 */
 	pci_write_config8(ctrl->d0f3, 0x64, 0xcc);
 	/* DIMM command / Address Selection */
 	pci_write_config8(ctrl->d0f3, 0x67, 0x00);
 	/* Disable cross bank/multi page mode */
 	pci_write_config8(ctrl->d0f3, 0x69, 0x00);
-	/* disable refresh now */
+	/* Disable refresh now */
 	pci_write_config8(ctrl->d0f3, 0x6a, 0x00);
 
-	/* frequency 100MHZ */
+	/* Frequency 100 MHz */
 	pci_write_config8(ctrl->d0f3, 0x90, 0x00);
 	pci_write_config8(ctrl->d0f2, 0x57, 0x18);
-	/* Allow manual dll reset */
+	/* Allow manual DLL reset */
 	pci_write_config8(ctrl->d0f3, 0x6b, 0x10);
 
 	/* Bank/Rank Interleave Address Select */
 	pci_write_config8(ctrl->d0f3, 0x52, 0x33);
 	pci_write_config8(ctrl->d0f3, 0x53, 0x3f);
-	
-	/* Set to DDR2 sdram, BL=8 (0xc8, 0xc0 for bl=4) */
+
+	/* Set to DDR2 SDRAM, BL=8 (0xc8, 0xc0 for bl=4) */
 	pci_write_config8(ctrl->d0f3, 0x6c, 0xc8);
 
 	/* DRAM Bus Turn-Around Setting */
 	pci_write_config8(ctrl->d0f3, 0x60, 0x03);
 	/* DRAM Arbitration Control */
 	pci_write_config8(ctrl->d0f3, 0x66, 0x80);
-	/* DQS Tuning: testing on a couple different boards has shown this is
+	/*
+	 * DQS Tuning: testing on a couple different boards has shown this is
 	 * static, or close enough that it can be. Which is good, because the
- 	 * tuning function used too many registers
+	 * tuning function used too many registers.
 	 */
-	/* DQS Output Delay for CHannel A */
+	/* DQS Output Delay for Channel A */
 	pci_write_config8(ctrl->d0f3, 0x70, 0x00);
 	/* MD Output Delay for Channel A */
 	pci_write_config8(ctrl->d0f3, 0x71, 0x01);
 	pci_write_config8(ctrl->d0f3, 0x73, 0x01);
 
-	/* dram arbitration timer */
+	/* DRAM arbitration timer */
 	pci_write_config8(ctrl->d0f3, 0x65, 0xd9);
 
-	/* dram signal timing control */
+	/* DRAM signal timing control */
 	pci_write_config8(ctrl->d0f3, 0x74, 0x01);
 	pci_write_config8(ctrl->d0f3, 0x75, 0x01);
 	pci_write_config8(ctrl->d0f3, 0x76, 0x06);
@@ -316,7 +317,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 	pci_write_config8(ctrl->d0f3, 0x7a, 0x00);
 	pci_write_config8(ctrl->d0f3, 0x7b, 0x10);
 
-	/* dram clocking control */
+	/* DRAM clocking control */
 	pci_write_config8(ctrl->d0f3, 0x91, 0x01);
 	/* CS/CKE Clock Phase Control */
 	pci_write_config8(ctrl->d0f3, 0x92, 0x02);
@@ -325,18 +326,18 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 	/* DCLKO Feedback Mode Output Control */
 	pci_write_config8(ctrl->d0f3, 0x94, 0x00);
 	pci_write_config8(ctrl->d0f3, 0x9d, 0x0f);
-	
+
 	/* SDRAM ODT Control */
 	pci_write_config8(ctrl->d0f3, 0xda, 0x80);
 	/* Channel A DQ/DQS CKG Output Delay Control */
 	pci_write_config8(ctrl->d0f3, 0xdc, 0x54);
 	/* Channel A DQ/DQS CKG Output Delay Control */
 	pci_write_config8(ctrl->d0f3, 0xdd, 0x55);
-	/* odt lookup table */
+	/* ODT lookup table */
 	pci_write_config8(ctrl->d0f3, 0xd8, 0x01);
 	pci_write_config8(ctrl->d0f3, 0xd9, 0x0a);
 
-	/* ddr sdram control */
+	/* DDR SDRAM control */
 	pci_write_config8(ctrl->d0f3, 0x6d, 0xc0);
 	pci_write_config8(ctrl->d0f3, 0x6f, 0x41);
 
@@ -344,7 +345,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 	pci_write_config8(ctrl->d0f3, 0xd0, 0xaa);
 
 	/* Compensation Control */
-	pci_write_config8(ctrl->d0f3, 0xd3, 0x01); /*enable auto compensation*/
+	pci_write_config8(ctrl->d0f3, 0xd3, 0x01); /* Enable autocompensation */
 	/* ODT (some are set with driving select above) */
 	pci_write_config8(ctrl->d0f3, 0xd4, 0x80);
 	pci_write_config8(ctrl->d0f3, 0xd5, 0x8a);
@@ -362,8 +363,8 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 	pci_write_config8(ctrl->d0f3, 0xee, 0x00);
 	/* DQS CKG Input Delay Control */
 	pci_write_config8(ctrl->d0f3, 0xef, 0x10);
-	
-	/* dram duty control */
+
+	/* DRAM duty control */
 	pci_write_config8(ctrl->d0f3, 0xed, 0x10);
 
 	/* SMM and APIC decoding, we do not use SMM */
@@ -372,23 +373,23 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 	/* SMM and APIC decoding mirror */
 	pci_write_config8(ctrl->d0f7, 0xe6, reg);
 
-	/* dram module configuration */
+	/* DRAM module configuration */
 	pci_write_config8(ctrl->d0f3, 0x6e, 0x89);
 }
 
 static void sdram_set_post(const struct mem_controller *ctrl)
 {
 	device_t dev = ctrl->d0f3;
+
 	/* Enable multipage mode. */
 	pci_write_config8(dev, 0x69, 0x03);
 
 	/* Enable refresh. */
 	pci_write_config8(dev, 0x6a, 0x32);
 
-	// vga device
-	pci_write_config16(dev, 0xa0, (1 <<15));
+	/* VGA device. */
+	pci_write_config16(dev, 0xa0, (1 << 15));
 	pci_write_config16(dev, 0xa4, 0x0010);
-	
 }
 
 static void sdram_enable(device_t dev, unsigned long rank_address)
@@ -410,33 +411,35 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
 	/* 3. Mode register set. */
 	PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
 	do_ram_command(dev, RAM_COMMAND_MRS);
-	read32(rank_address + 0x120000);// EMRS DLL Enable
-	read32(rank_address + 0x800); 	// MRS DLL Reset
-	
+	read32(rank_address + 0x120000);	/* EMRS DLL Enable */
+	read32(rank_address + 0x800);		/* MRS DLL Reset */
+
 	/* 4. Precharge all again. */
 	PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n");
 	do_ram_command(dev, RAM_COMMAND_PRECHARGE);
 	read32(rank_address + 0x0);
-	
+
 	/* 5. Perform 8 refresh cycles. Wait tRC each time. */
 	PRINT_DEBUG_MEM("RAM Enable 3: CBR\r\n");
 	do_ram_command(dev, RAM_COMMAND_CBR);
-	for(i = 0; i < 8; i++) {
+	for (i = 0; i < 8; i++) {
 		read32(rank_address + 0x20);
 		udelay(100);
 	}
 
 	/* 6. Mode register set. */
 	PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
-	//safe value for now, BL=8, WR=5, CAS=4
-	/* (E)MRS values are from the BPG. No direct explanation is given, but 
+	/* Safe value for now, BL=8, WR=5, CAS=4 */
+	/*
+	 * (E)MRS values are from the BPG. No direct explanation is given, but 
 	 * they should somehow conform to the JEDEC DDR2 SDRAM Specification
-	 * (JESD79-2C). */
+	 * (JESD79-2C).
+	 */
 	do_ram_command(dev, RAM_COMMAND_MRS);
-	read32(rank_address + 0x002258);	// MRS command
-	read32(rank_address + 0x121c20);	// EMRS OCD Default
-	read32(rank_address + 0x120020);	// EMRS OCD Calibration Mode Exit
-	
+	read32(rank_address + 0x002258); /* MRS command */
+	read32(rank_address + 0x121c20); /* EMRS OCD Default */
+	read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */
+
 	/* 8. Normal operation */
 	PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\r\n");
 	do_ram_command(dev, RAM_COMMAND_NORMAL);
@@ -444,7 +447,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
 }
 
 /*
- * Support one dimm with up to 2 ranks
+ * Support one DIMM with up to 2 ranks.
  */
 static void ddr_ram_setup(const struct mem_controller *ctrl)
 {
@@ -456,7 +459,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 	sdram_enable(ctrl->d0f3, 0);
 	reg = pci_read_config8(ctrl->d0f3, 0x41);
 	if (reg != 0)
-		sdram_enable(ctrl->d0f3, pci_read_config8(ctrl->d0f3, 0x40) << 26);
+		sdram_enable(ctrl->d0f3,
+			     pci_read_config8(ctrl->d0f3, 0x40) << 26);
 	sdram_set_post(ctrl);
 }
-