3 files changed, 0 insertions, 9 deletions
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c
index cf1da63f85..e6a344e738 100644
--- a/src/northbridge/intel/pineview/romstage.c
+++ b/src/northbridge/intel/pineview/romstage.c
@@ -18,7 +18,6 @@
  */
 
 #include <arch/io.h>
-#include <lib.h>
 #include <timestamp.h>
 #include <console/console.h>
 #include <device/pci_ops.h>
@@ -105,8 +104,6 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	post_code(0x31);
 
-	quick_ram_check();
-
 	mb_pirq_setup();
 
 	rcba_config();
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 3f62d10a1c..4a048db7c7 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -31,7 +31,6 @@
 #include <southbridge/intel/common/smbus.h>
 #include <cpu/x86/msr.h>
 #include <delay.h>
-#include <lib.h>
 #include "raminit_native.h"
 #include "raminit_common.h"
 #include "sandybridge.h"
@@ -419,9 +418,6 @@ static void init_dram_ddr3(int min_tck, int s3resume)
 	/* Zone config */
 	dram_zones(&ctrl, 0);
 
-	/* Non intrusive, fast ram check */
-	quick_ram_check();
-
 	intel_early_me_status();
 	intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
 	intel_early_me_status();
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 72ef1a915e..02a8b74f70 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -23,7 +23,6 @@
 #include <arch/cpu.h>
 #include <delay.h>
 #include <halt.h>
-#include <lib.h>
 #include "iomap.h"
 #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
 #include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */
@@ -734,6 +733,5 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
 	}
 
 	timestamp_add_now(TS_AFTER_INITRAM);
-	quick_ram_check();
 	printk(BIOS_DEBUG, "Memory initialized\n");
 }