diff options
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/pei_data.h | 27 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/raminit.c | 63 |
2 files changed, 6 insertions, 84 deletions
diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index 8c907c1db8..280c73b75a 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -31,7 +31,8 @@ #define PEI_DATA_H typedef void (*tx_byte_func)(unsigned char byte); -#define PEI_VERSION 4 +#define PEI_VERSION 10 + struct pei_data { uint32_t pei_version; @@ -46,11 +47,10 @@ struct pei_data uint32_t rcba; uint32_t pmbase; uint32_t gpiobase; - uint32_t thermalbase; + uint32_t temp_mmio_base; uint32_t system_type; // 0 Mobile, 1 Desktop/Server uint32_t tseg_size; uint8_t spd_addresses[4]; - uint8_t ts_addresses[4]; int boot_mode; int ec_present; // 0 = leave channel enabled @@ -59,9 +59,6 @@ struct pei_data // 3 = disable dimm 0+1 on channel int dimm_channel0_disabled; int dimm_channel1_disabled; - /* Seed values saved in CMOS */ - uint32_t scrambler_seed; - uint32_t scrambler_seed_s3; /* Data read from flash and passed into MRC */ unsigned char *mrc_input; unsigned int mrc_input_len; @@ -69,9 +66,9 @@ struct pei_data unsigned char *mrc_output; unsigned int mrc_output_len; /* - * Max frequency DDR3 could be ran at. Could be one of four values: - * 800, 1067, 1333, 1600 - */ + * Max frequency DDR3 could be ran at. Could be one of four values: 800, + * 1067, 1333, 1600 + */ uint32_t max_ddr3_freq; /* * USB Port Configuration: @@ -98,18 +95,6 @@ struct pei_data */ uint8_t spd_data[4][256]; tx_byte_func tx_byte; - int ddr3lv_support; - /* pcie_init needs to be set to 1 to have the system agent initialize - * PCIe. Note: This should only be required if your system has Gen3 devices - * and it will increase your boot time by at least 100ms. - */ - int pcie_init; - /* N mode functionality. Leave this setting at 0. - * 0 Auto - * 1 1N - * 2 2N - */ - int nmode; } __attribute__((packed)); #endif diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index b45682596e..09c8fc4d78 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -40,25 +40,8 @@ #define recovery_mode_enabled(x) 0 #endif -/* - * MRC scrambler seed offsets should be reserved in - * mainboard cmos.layout and not covered by checksum. - */ -#if CONFIG_USE_OPTION_TABLE -#include "option_table.h" -#define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3) -#define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3) -#define CMOS_OFFSET_MRC_SEED_CHK (CMOS_VSTART_mrc_scrambler_seed_chk >> 3) -#else -#define CMOS_OFFSET_MRC_SEED 152 -#define CMOS_OFFSET_MRC_SEED_S3 156 -#define CMOS_OFFSET_MRC_SEED_CHK 160 -#endif - static void save_mrc_data(struct pei_data *pei_data) { - u16 c1, c2, checksum; - #if CONFIG_EARLY_CBMEM_INIT struct mrc_data_container *mrcdata; int output_len = ALIGN(pei_data->mrc_output_len, 16); @@ -86,62 +69,16 @@ static void save_mrc_data(struct pei_data *pei_data) mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data, mrcdata->mrc_data_size); #endif - - /* Save the MRC seed values to CMOS */ - cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); - printk(BIOS_DEBUG, "Save scrambler seed 0x%08x to CMOS 0x%02x\n", - pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); - - cmos_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); - printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", - pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); - - /* Save a simple checksum of the seed values */ - c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, - sizeof(u32)); - c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3, - sizeof(u32)); - checksum = add_ip_checksums(sizeof(u32), c1, c2); - - cmos_write(checksum & 0xff, CMOS_OFFSET_MRC_SEED_CHK); - cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK+1); } static void prepare_mrc_cache(struct pei_data *pei_data) { struct mrc_data_container *mrc_cache; - u16 c1, c2, checksum, seed_checksum; // preset just in case there is an error pei_data->mrc_input = NULL; pei_data->mrc_input_len = 0; - /* Read scrambler seeds from CMOS */ - pei_data->scrambler_seed = cmos_read32(CMOS_OFFSET_MRC_SEED); - printk(BIOS_DEBUG, "Read scrambler seed 0x%08x from CMOS 0x%02x\n", - pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); - - pei_data->scrambler_seed_s3 = cmos_read32(CMOS_OFFSET_MRC_SEED_S3); - printk(BIOS_DEBUG, "Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", - pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); - - /* Compute seed checksum and compare */ - c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, - sizeof(u32)); - c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3, - sizeof(u32)); - checksum = add_ip_checksums(sizeof(u32), c1, c2); - - seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK); - seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK+1) << 8; - - if (checksum != seed_checksum) { - printk(BIOS_ERR, "%s: invalid seed checksum\n", __func__); - pei_data->scrambler_seed = 0; - pei_data->scrambler_seed_s3 = 0; - return; - } - if ((mrc_cache = find_current_mrc_cache()) == NULL) { /* error message printed in find_current_mrc_cache */ return; |