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-rw-r--r--src/northbridge/intel/fsp_sandybridge/Kconfig4
-rw-r--r--src/northbridge/intel/nehalem/northbridge.c2
-rw-r--r--src/northbridge/intel/sandybridge/northbridge.c2
3 files changed, 0 insertions, 8 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig
index 0c3d5f5156..ce366ef1ba 100644
--- a/src/northbridge/intel/fsp_sandybridge/Kconfig
+++ b/src/northbridge/intel/fsp_sandybridge/Kconfig
@@ -87,14 +87,10 @@ config CBFS_SIZE
config ENABLE_FAST_BOOT
bool "Enable Fast Boot"
default y if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X
- depends on !CACHE_ROM
help
Enabling this feature will cause MRC data to be cached in NV storage
which will speed up boot time on future reboots and/or power cycles.
- WARNING: This feature combined with the CACHE_ROM may result in undefined
- behavior.
-
config MRC_CACHE_SIZE
hex "MRC Data Cache Size"
default 0x10000
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index f9386dedcc..d94bc09ba8 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -340,8 +340,6 @@ static const struct pci_driver mc_driver_44 __pci_driver = {
static void cpu_bus_init(device_t dev)
{
initialize_cpus(dev->link_list);
- /* Enable ROM caching if option was selected. */
- x86_mtrr_enable_rom_caching();
}
static void cpu_bus_noop(device_t dev)
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 7db9301c30..5440140089 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -476,8 +476,6 @@ static const struct pci_driver mc_driver_1 __pci_driver = {
static void cpu_bus_init(device_t dev)
{
initialize_cpus(dev->link_list);
- /* Enable ROM caching if option was selected. */
- x86_mtrr_enable_rom_caching();
}
static void cpu_bus_noop(device_t dev)