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-rw-r--r--src/northbridge/intel/e7505/northbridge.c8
-rw-r--r--src/northbridge/intel/gm45/northbridge.c14
-rw-r--r--src/northbridge/intel/haswell/northbridge.c14
-rw-r--r--src/northbridge/intel/i440bx/northbridge.c4
-rw-r--r--src/northbridge/intel/i945/northbridge.c14
-rw-r--r--src/northbridge/intel/ironlake/northbridge.c20
-rw-r--r--src/northbridge/intel/pineview/northbridge.c18
-rw-r--r--src/northbridge/intel/sandybridge/northbridge.c22
-rw-r--r--src/northbridge/intel/x4x/northbridge.c14
9 files changed, 64 insertions, 64 deletions
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index fb4d3e37a8..faa46e0d8a 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -39,14 +39,14 @@ static void mch_domain_read_resources(struct device *dev)
/* Report the memory regions */
idx = 10;
- ram_resource(dev, idx++, 0, tolmk);
- mmio_resource(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
+ ram_resource_kb(dev, idx++, 0, tolmk);
+ mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
if (tomk > basek_4G)
- ram_resource(dev, idx++, basek_4G, tomk - basek_4G);
+ ram_resource_kb(dev, idx++, basek_4G, tomk - basek_4G);
if (remaplimitk > remapbasek)
- ram_resource(dev, idx++, remapbasek, remaplimitk - remapbasek);
+ ram_resource_kb(dev, idx++, remapbasek, remaplimitk - remapbasek);
}
static void mch_domain_set_resources(struct device *dev)
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 83039a8c81..d2a8742660 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -103,7 +103,7 @@ static void mch_domain_read_resources(struct device *dev)
printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);
/* Report lowest memory region */
- ram_resource(dev, idx++, 0, 0xa0000 / KiB);
+ ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB);
/*
* Reserve everything between A segment and 1MB:
@@ -111,11 +111,11 @@ static void mch_domain_read_resources(struct device *dev)
* 0xa0000 - 0xbffff: Legacy VGA
* 0xc0000 - 0xfffff: RAM
*/
- mmio_resource(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
- reserved_ram_resource(dev, idx++, 0xc0000 / KiB, (1*MiB - 0xc0000) / KiB);
+ mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
+ reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, (1*MiB - 0xc0000) / KiB);
/* Report < 4GB memory */
- ram_resource(dev, idx++, 1*MiB / KiB, tomk - 1*MiB / KiB);
+ ram_resource_kb(dev, idx++, 1*MiB / KiB, tomk - 1*MiB / KiB);
/*
* If >= 4GB installed then memory from TOLUD to 4GB
@@ -123,15 +123,15 @@ static void mch_domain_read_resources(struct device *dev)
*/
touud >>= 10; /* Convert to KB */
if (touud > 4096 * 1024) {
- ram_resource(dev, idx++, 4096 * 1024, touud - (4096 * 1024));
+ ram_resource_kb(dev, idx++, 4096 * 1024, touud - (4096 * 1024));
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
(touud >> 10) - 4096);
}
printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx "
"size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10);
- /* Don't use uma_resource() as our UMA touches the PCI hole. */
- fixed_mem_resource(dev, idx++, tomk, uma_sizek, IORESOURCE_RESERVE);
+ /* Don't use uma_resource_kb() as our UMA touches the PCI hole. */
+ fixed_mem_resource_kb(dev, idx++, tomk, uma_sizek, IORESOURCE_RESERVE);
mmconf_resource(dev, idx++);
}
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 5e57f9d618..606461b4e7 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -287,13 +287,13 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
/* 0 - > 0xa0000 */
base_k = 0;
size_k = (0xa0000 >> 10) - base_k;
- ram_resource(dev, index++, base_k, size_k);
+ ram_resource_kb(dev, index++, base_k, size_k);
/* 0xc0000 -> TSEG - DPR */
base_k = 0xc0000 >> 10;
size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k;
size_k -= dpr.size * MiB / KiB;
- ram_resource(dev, index++, base_k, size_k);
+ ram_resource_kb(dev, index++, base_k, size_k);
/* TSEG - DPR -> BGSM */
resource = new_resource(dev, index++);
@@ -316,15 +316,15 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
touud_k = mc_values[TOUUD_REG] >> 10;
size_k = touud_k - base_k;
if (touud_k > base_k)
- ram_resource(dev, index++, base_k, size_k);
+ ram_resource_kb(dev, index++, base_k, size_k);
/* Reserve everything between A segment and 1MB:
*
* 0xa0000 - 0xbffff: Legacy VGA
* 0xc0000 - 0xfffff: RAM
*/
- mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
- reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);
+ mmio_resource_kb(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
+ reserved_ram_resource_kb(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);
*resource_cnt = index;
}
@@ -342,8 +342,8 @@ static void mc_read_resources(struct device *dev)
/* Add VT-d MMIO resources, if capable */
if (vtd_capable) {
- mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB);
- mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB);
+ mmio_resource_kb(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB);
+ mmio_resource_kb(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB);
}
/* Calculate and add DRAM resources */
diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c
index 618141b35f..7162bb7126 100644
--- a/src/northbridge/intel/i440bx/northbridge.c
+++ b/src/northbridge/intel/i440bx/northbridge.c
@@ -61,8 +61,8 @@ static void i440bx_domain_read_resources(struct device *dev)
/* Report the memory regions. */
idx = 10;
- ram_resource(dev, idx++, 0, 640);
- ram_resource(dev, idx++, 768, tolmk - 768);
+ ram_resource_kb(dev, idx++, 0, 640);
+ ram_resource_kb(dev, idx++, 768, tolmk - 768);
}
}
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index a111378fd8..5524b315c5 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -75,15 +75,15 @@ static void mch_domain_read_resources(struct device *dev)
printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk_stolen / KiB));
/* Report the memory regions */
- ram_resource(dev, idx++, 0, 0xa0000 / KiB);
- ram_resource(dev, idx++, 1 * MiB / KiB, (tomk - 1 * MiB / KiB));
- uma_resource(dev, idx++, uma_memory_base / KiB, uma_memory_size / KiB);
- mmio_resource(dev, idx++, tseg_memory_base / KiB, tseg_memory_size / KiB);
- uma_resource(dev, idx++, cbmem_topk, delta_cbmem);
+ ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB);
+ ram_resource_kb(dev, idx++, 1 * MiB / KiB, (tomk - 1 * MiB / KiB));
+ uma_resource_kb(dev, idx++, uma_memory_base / KiB, uma_memory_size / KiB);
+ mmio_resource_kb(dev, idx++, tseg_memory_base / KiB, tseg_memory_size / KiB);
+ uma_resource_kb(dev, idx++, cbmem_topk, delta_cbmem);
/* legacy VGA memory */
- mmio_resource(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
+ mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
/* RAM to be used for option roms and BIOS */
- reserved_ram_resource(dev, idx++, 0xc0000 / KiB, (1 * MiB - 0xc0000) / KiB);
+ reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, (1 * MiB - 0xc0000) / KiB);
}
static void mch_domain_set_resources(struct device *dev)
diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c
index b74909faf3..d2f5c79fe1 100644
--- a/src/northbridge/intel/ironlake/northbridge.c
+++ b/src/northbridge/intel/ironlake/northbridge.c
@@ -54,8 +54,8 @@ static void add_fixed_resources(struct device *dev, int index)
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
- mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 / KiB) - legacy_hole_base_k);
- reserved_ram_resource(dev, index++, 0xc0000 / KiB, (0x100000 - 0xc0000) / KiB);
+ mmio_resource_kb(dev, index++, legacy_hole_base_k, (0xc0000 / KiB) - legacy_hole_base_k);
+ reserved_ram_resource_kb(dev, index++, 0xc0000 / KiB, (0x100000 - 0xc0000) / KiB);
}
#if CONFIG(HAVE_ACPI_TABLES)
@@ -105,10 +105,10 @@ static void mc_read_resources(struct device *dev)
printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)touud);
/* Report the memory regions */
- ram_resource(dev, index++, 0, 0xa0000 / KiB);
- ram_resource(dev, index++, 1 * MiB / KiB, (tseg_base - 1 * MiB) / KiB);
+ ram_resource_kb(dev, index++, 0, 0xa0000 / KiB);
+ ram_resource_kb(dev, index++, 1 * MiB / KiB, (tseg_base - 1 * MiB) / KiB);
- mmio_resource(dev, index++, tseg_base / KiB, CONFIG_SMM_TSEG_SIZE / KiB);
+ mmio_resource_kb(dev, index++, tseg_base / KiB, CONFIG_SMM_TSEG_SIZE / KiB);
reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC);
const int uma_sizes_gtt[16] =
@@ -130,17 +130,17 @@ static void mc_read_resources(struct device *dev)
if (gtt_base > tseg_end) {
/* Reserve the gap. MMIO doesn't work in this range. Keep
it uncacheable, though, for easier MTRR allocation. */
- mmio_resource(dev, index++, tseg_end / KiB, (gtt_base - tseg_end) / KiB);
+ mmio_resource_kb(dev, index++, tseg_end / KiB, (gtt_base - tseg_end) / KiB);
}
- mmio_resource(dev, index++, gtt_base / KiB, uma_size_gtt * KiB);
- mmio_resource(dev, index++, igd_base / KiB, uma_size_igd * KiB);
+ mmio_resource_kb(dev, index++, gtt_base / KiB, uma_size_gtt * KiB);
+ mmio_resource_kb(dev, index++, igd_base / KiB, uma_size_igd * KiB);
if (touud > 4096)
- ram_resource(dev, index++, (4096 * KiB), ((touud - 4096) * KiB));
+ ram_resource_kb(dev, index++, (4096 * KiB), ((touud - 4096) * KiB));
/* This memory is not DMA-capable. */
if (touud >= 8192 - 64)
- bad_ram_resource(dev, index++, 0x1fc000000ULL / KiB, 0x004000000 / KiB);
+ bad_ram_resource_kb(dev, index++, 0x1fc000000ULL / KiB, 0x004000000 / KiB);
add_fixed_resources(dev, index);
}
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index 9e272235d2..4a5a91823d 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -35,8 +35,8 @@ static void add_fixed_resources(struct device *dev, int index)
| IORESOURCE_STORED
| IORESOURCE_ASSIGNED;
- mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 / KiB) - legacy_hole_base_k);
- reserved_ram_resource(dev, index++, 0xc0000 / KiB, (0x100000 - 0xc0000) / KiB);
+ mmio_resource_kb(dev, index++, legacy_hole_base_k, (0xc0000 / KiB) - legacy_hole_base_k);
+ reserved_ram_resource_kb(dev, index++, 0xc0000 / KiB, (0x100000 - 0xc0000) / KiB);
}
static void mch_domain_read_resources(struct device *dev)
@@ -98,12 +98,12 @@ static void mch_domain_read_resources(struct device *dev)
printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOMK: 0x%xK\n", delta_cbmem);
/* Report the memory regions */
- ram_resource(dev, index++, 0, 0xa0000 / KiB);
- ram_resource(dev, index++, 1 * MiB / KiB, tomk - 1 * MiB / KiB);
- mmio_resource(dev, index++, tseg_basek, tseg_sizek);
- mmio_resource(dev, index++, gtt_basek, gsm_sizek);
- mmio_resource(dev, index++, igd_basek, gms_sizek);
- reserved_ram_resource(dev, index++, cbmem_topk, delta_cbmem);
+ ram_resource_kb(dev, index++, 0, 0xa0000 / KiB);
+ ram_resource_kb(dev, index++, 1 * MiB / KiB, tomk - 1 * MiB / KiB);
+ mmio_resource_kb(dev, index++, tseg_basek, tseg_sizek);
+ mmio_resource_kb(dev, index++, gtt_basek, gsm_sizek);
+ mmio_resource_kb(dev, index++, igd_basek, gms_sizek);
+ reserved_ram_resource_kb(dev, index++, cbmem_topk, delta_cbmem);
/*
* If > 4GB installed then memory from TOLUD to 4GB
@@ -111,7 +111,7 @@ static void mch_domain_read_resources(struct device *dev)
*/
touud >>= 10; /* Convert to KB */
if (touud > top32memk) {
- ram_resource(dev, index++, top32memk, touud - top32memk);
+ ram_resource_kb(dev, index++, top32memk, touud - top32memk);
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
(touud - top32memk) / KiB);
}
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 1bc812ab29..032e500dc3 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -64,23 +64,23 @@ static struct device_operations pci_domain_ops = {
static void add_fixed_resources(struct device *dev, int index)
{
- mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
+ mmio_resource_kb(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
- mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k);
+ mmio_resource_kb(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k);
- reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10);
+ reserved_ram_resource_kb(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10);
if (is_sandybridge()) {
/* Required for SandyBridge sighting 3715511 */
- bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);
- bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10);
+ bad_ram_resource_kb(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);
+ bad_ram_resource_kb(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10);
}
/* Reserve IOMMU BARs */
const u32 capid0_a = pci_read_config32(dev, CAPID0_A);
if (!(capid0_a & (1 << 23))) {
- mmio_resource(dev, index++, GFXVT_BASE >> 10, 4);
- mmio_resource(dev, index++, VTVC0_BASE >> 10, 4);
+ mmio_resource_kb(dev, index++, GFXVT_BASE >> 10, 4);
+ mmio_resource_kb(dev, index++, VTVC0_BASE >> 10, 4);
}
}
@@ -200,15 +200,15 @@ static void mc_read_resources(struct device *dev)
dpr_size_k = dpr.size * MiB / KiB;
tomk -= dpr_size_k;
dpr_base_k = (tseg_base - dpr.size * MiB) / KiB;
- reserved_ram_resource(dev, index++, dpr_base_k, dpr_size_k);
+ reserved_ram_resource_kb(dev, index++, dpr_base_k, dpr_size_k);
printk(BIOS_DEBUG, "DPR base 0x%08x size %uM\n", dpr_base_k * KiB, dpr.size);
}
printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10);
/* Report the memory regions */
- ram_resource(dev, index++, 0, legacy_hole_base_k);
- ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k,
+ ram_resource_kb(dev, index++, 0, legacy_hole_base_k);
+ ram_resource_kb(dev, index++, legacy_hole_base_k + legacy_hole_size_k,
(tomk - (legacy_hole_base_k + legacy_hole_size_k)));
/*
@@ -217,7 +217,7 @@ static void mc_read_resources(struct device *dev)
*/
touud >>= 10; /* Convert to KB */
if (touud > 4096 * 1024) {
- ram_resource(dev, index++, 4096 * 1024, touud - (4096 * 1024));
+ ram_resource_kb(dev, index++, 4096 * 1024, touud - (4096 * 1024));
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (touud >> 10) - 4096);
}
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index c92fd452bd..5b61224b55 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -81,12 +81,12 @@ static void mch_domain_read_resources(struct device *dev)
printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);
/* Report the memory regions */
- ram_resource(dev, index++, 0, legacy_hole_base_k);
- mmio_resource(dev, index++, legacy_hole_base_k,
+ ram_resource_kb(dev, index++, 0, legacy_hole_base_k);
+ mmio_resource_kb(dev, index++, legacy_hole_base_k,
(0xc0000 >> 10) - legacy_hole_base_k);
- reserved_ram_resource(dev, index++, 0xc0000 >> 10,
+ reserved_ram_resource_kb(dev, index++, 0xc0000 >> 10,
(0x100000 - 0xc0000) >> 10);
- ram_resource(dev, index++, 0x100000 >> 10, (tomk - (0x100000 >> 10)));
+ ram_resource_kb(dev, index++, 0x100000 >> 10, (tomk - (0x100000 >> 10)));
/*
* If >= 4GB installed then memory from TOLUD to 4GB
@@ -94,17 +94,17 @@ static void mch_domain_read_resources(struct device *dev)
*/
touud >>= 10; /* Convert to KB */
if (touud > top32memk) {
- ram_resource(dev, index++, top32memk, touud - top32memk);
+ ram_resource_kb(dev, index++, top32memk, touud - top32memk);
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
(touud - top32memk) >> 10);
}
printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x size=0x%08x\n",
tomk << 10, uma_sizek << 10);
- uma_resource(dev, index++, tomk, uma_sizek);
+ uma_resource_kb(dev, index++, tomk, uma_sizek);
/* Reserve high memory where the NB BARs are up to 4GiB */
- fixed_mem_resource(dev, index++, DEFAULT_HECIBAR >> 10,
+ fixed_mem_resource_kb(dev, index++, DEFAULT_HECIBAR >> 10,
top32memk - (DEFAULT_HECIBAR >> 10),
IORESOURCE_RESERVE);
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-23 17:16:32 +0000