diff options
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/i945/Kconfig | 9 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/acpi/i945.asl | 7 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 14 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/i945.h | 14 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/memmap.h | 12 |
5 files changed, 21 insertions, 35 deletions
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 23369e7da3..484b69482e 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -80,4 +80,13 @@ config MAX_CPUS int default 4 +config FIXED_MCHBAR_MMIO_BASE + default 0xfed14000 + +config FIXED_DMIBAR_MMIO_BASE + default 0xfed18000 + +config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + endif diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 349234b1fa..683ad375a5 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include "hostbridge.asl" -#include "../i945.h" /* Operating System Capabilities Method */ Method (_OSC, 4) @@ -38,9 +37,9 @@ Device (PDRC) Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 4564ff4bbb..b91afda187 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -143,9 +143,9 @@ static void i945_setup_bars(void) printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1); /* vram size from CMOS option */ @@ -715,7 +715,7 @@ static void i945_setup_root_complex_topology(void) EPBAR32(EPLE1D) |= (1 << 16) | (1 << 0); - EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; + EPBAR32(EPLE1A) = CONFIG_FIXED_DMIBAR_MMIO_BASE; EPBAR32(EPLE2D) |= (1 << 16) | (1 << 0); @@ -734,11 +734,11 @@ static void i945_setup_root_complex_topology(void) DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0); - DMIBAR32(DMILE2A) = DEFAULT_EPBAR; + DMIBAR32(DMILE2A) = CONFIG_FIXED_EPBAR_MMIO_BASE; /* PCI Express x16 Port Root Topology */ if (pci_read_config8(HOST_BRIDGE, DEVEN) & DEVEN_D1F0) { - pci_write_config32(p2peg, LE1A, DEFAULT_EPBAR); + pci_write_config32(p2peg, LE1A, CONFIG_FIXED_EPBAR_MMIO_BASE); pci_or_config32(p2peg, LE1D, 1 << 0); } } @@ -751,7 +751,7 @@ static void ich7_setup_root_complex_topology(void) RCBA32(ULD) |= (1 << 24) | (1 << 16); - RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR; + RCBA32(ULBA) = CONFIG_FIXED_DMIBAR_MMIO_BASE; /* Write ESD.CID to TCID */ RCBA32(RP1D) |= (2 << 16); RCBA32(RP2D) |= (2 << 16); diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index b3c28aebd1..fe06afc8ec 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -3,7 +3,7 @@ #ifndef NORTHBRIDGE_INTEL_I945_H #define NORTHBRIDGE_INTEL_I945_H -#include "memmap.h" +#define DEFAULT_X60BAR 0xfed13000 #include <southbridge/intel/i82801gx/i82801gx.h> @@ -90,9 +90,7 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#include <northbridge/intel/common/fixed_bars.h> /* Chipset Control Registers */ #define FSBPMC3 0x40 /* 32bit */ @@ -274,10 +272,6 @@ * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) - #define EPPVCCAP1 0x004 /* 32bit */ #define EPPVCCAP2 0x008 /* 32bit */ @@ -305,10 +299,6 @@ * DMIBAR */ -#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) - #define DMIVCECH 0x000 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */ #define DMIPVCCAP2 0x008 /* 32bit */ diff --git a/src/northbridge/intel/i945/memmap.h b/src/northbridge/intel/i945/memmap.h deleted file mode 100644 index fcda4474bd..0000000000 --- a/src/northbridge/intel/i945/memmap.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef NORTHBRIDGE_INTEL_I945_MEMMAP_H -#define NORTHBRIDGE_INTEL_I945_MEMMAP_H - -/* Northbridge BARs */ -#define DEFAULT_X60BAR 0xfed13000 -#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ - -#endif |