summaryrefslogtreecommitdiff
path: root/src/northbridge/intel
diff options
context:
space:
mode:
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/sandybridge/romstage.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 3bfefb9fc7..3e128cdff3 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -28,7 +28,6 @@
#include <device/pci_def.h>
#include <device/device.h>
#include <halt.h>
-#include <security/tpm/tspi.h>
#include <northbridge/intel/sandybridge/chip.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
@@ -117,8 +116,5 @@ void mainboard_romstage_entry(unsigned long bist)
northbridge_romstage_finalize(s3resume);
- if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
- tpm_setup(s3resume);
-
post_code(0x3f);
}