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-rwxr-xr-x[-rw-r--r--]src/northbridge/intel/fsp_rangeley/chip.h25
1 files changed, 13 insertions, 12 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h
index d3828c7764..a8d0a1f137 100644..100755
--- a/src/northbridge/intel/fsp_rangeley/chip.h
+++ b/src/northbridge/intel/fsp_rangeley/chip.h
@@ -52,21 +52,22 @@ struct northbridge_intel_fsp_rangeley_config {
/* Enable the Rank Margin Tool, needs PrintDebugMessages */
uint8_t MrcRmtSupport;
-#define BIFURCATION_4_4_4_4 0
-#define BIFURCATION_4_4_8 1
-#define BIFURCATION_8_4_4 2
-#define BIFURCATION_8_8 3
-#define BIFURCATION_16 4
+ /* PCIe port bifurcation control */
uint8_t Bifurcation;
+ #define BIFURCATION_4_4_4_4 0
+ #define BIFURCATION_4_4_8 1
+ #define BIFURCATION_8_4_4 2
+ #define BIFURCATION_8_8 3
+ #define BIFURCATION_16 4
/* PCIe port de-emphasis control */
- #define DE_EMPHASIS_DEFAULT 0
- #define DE_EMPHASIS_MINUS_6_0_DB 1
- #define DE_EMPHASIS_MINUS_3_5_DB 2
- uint8_t PcdPcieRootPort1DeEmphasis;
- uint8_t PcdPcieRootPort2DeEmphasis;
- uint8_t PcdPcieRootPort3DeEmphasis;
- uint8_t PcdPcieRootPort4DeEmphasis;
+ uint8_t PcdPcieRootPort1DeEmphasis;
+ uint8_t PcdPcieRootPort2DeEmphasis;
+ uint8_t PcdPcieRootPort3DeEmphasis;
+ uint8_t PcdPcieRootPort4DeEmphasis;
+ #define DE_EMPHASIS_DEFAULT 0
+ #define DE_EMPHASIS_MINUS_6_0_DB 1
+ #define DE_EMPHASIS_MINUS_3_5_DB 2
};
#endif