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-rw-r--r--src/northbridge/intel/i945/Kconfig1
-rw-r--r--src/northbridge/intel/i945/northbridge.c22
2 files changed, 2 insertions, 21 deletions
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 92bf65279d..996e1d9d4d 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -30,6 +30,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select POSTCAR_STAGE
select POSTCAR_CONSOLE
select SMM_TSEG
+ select PARALLEL_MP
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
def_bool n
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 10a7ba4906..7c209dc32f 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -165,26 +165,6 @@ void northbridge_write_smram(u8 smram)
pci_write_config8(dev, SMRAM, smram);
}
-/*
- * Really doesn't belong here but will go away with parallel mp init,
- * so let it be here for a while...
- */
-int cpu_get_apic_id_map(int *apic_id_map)
-{
- unsigned int i;
-
- /* Logical processors (threads) per core */
- const struct cpuid_result cpuid1 = cpuid(1);
- /* Read number of cores. */
- const char cores = (cpuid1.ebx >> 16) & 0xf;
-
- /* TODO in parallel MP cpuid(1).ebx */
- for (i = 0; i < cores; i++)
- apic_id_map[i] = i;
-
- return cores;
-}
-
/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
* See e7525/northbridge.c for an example.
@@ -249,7 +229,7 @@ static const struct pci_driver mc_driver __pci_driver = {
static void cpu_bus_init(struct device *dev)
{
- initialize_cpus(dev->link_list);
+ bsp_init_and_start_aps(dev->link_list);
}
static struct device_operations cpu_bus_ops = {