diff options
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/nehalem/early_init.c | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 3 |
2 files changed, 2 insertions, 4 deletions
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 1f413e3ad1..5bdb5d5e0a 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -139,8 +139,7 @@ void nehalem_early_initialization(int chipset_type) s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3); - if (CONFIG(ELOG_BOOT_COUNT) && !s3_resume) - boot_count_increment(); + elog_boot_notify(s3_resume); /* Device Enable */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 1b402dcc56..55f2928213 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -74,8 +74,7 @@ void mainboard_romstage_entry(void) s3resume = southbridge_detect_s3_resume(); - if (CONFIG(ELOG_BOOT_COUNT) && !s3resume) - boot_count_increment(); + elog_boot_notify(s3resume); post_code(0x38); |