summaryrefslogtreecommitdiff
path: root/src/northbridge/intel
diff options
context:
space:
mode:
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/pineview/raminit.c19
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.c33
2 files changed, 27 insertions, 25 deletions
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 7f59d9197b..720bd6436e 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -17,6 +17,7 @@
#include <cf9_reset.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
+#include <commonlib/helpers.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <delay.h>
@@ -364,15 +365,15 @@ static void sdram_detect_smallest_params(struct sysinfo *s)
u32 maxtrtp = 0;
FOR_EACH_POPULATED_DIMM(s->dimms, i) {
- maxtras = max(maxtras, s->dimms[i].spd_data[30] * 1000);
- maxtrp = max(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2);
- maxtrcd = max(maxtrcd, (s->dimms[i].spd_data[29] * 1000) >> 2);
- maxtwr = max(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2);
- maxtrfc = max(maxtrfc, s->dimms[i].spd_data[42] * 1000 +
+ maxtras = MAX(maxtras, s->dimms[i].spd_data[30] * 1000);
+ maxtrp = MAX(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2);
+ maxtrcd = MAX(maxtrcd, (s->dimms[i].spd_data[29] * 1000) >> 2);
+ maxtwr = MAX(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2);
+ maxtrfc = MAX(maxtrfc, s->dimms[i].spd_data[42] * 1000 +
(s->dimms[i].spd_data[40] & 0xf));
- maxtwtr = max(maxtwtr, (s->dimms[i].spd_data[37] * 1000) >> 2);
- maxtrrd = max(maxtrrd, (s->dimms[i].spd_data[28] * 1000) >> 2);
- maxtrtp = max(maxtrtp, (s->dimms[i].spd_data[38] * 1000) >> 2);
+ maxtwtr = MAX(maxtwtr, (s->dimms[i].spd_data[37] * 1000) >> 2);
+ maxtrrd = MAX(maxtrrd, (s->dimms[i].spd_data[28] * 1000) >> 2);
+ maxtrtp = MAX(maxtrtp, (s->dimms[i].spd_data[38] * 1000) >> 2);
}
/*
* TODO: on ddr3 there might be some minimal required values for some
@@ -456,7 +457,7 @@ static void sdram_detect_ram_speed(struct sysinfo *s)
// Start with fastest common CAS
cas = 0;
highcas = msbp;
- lowcas = max(lsbp, 5);
+ lowcas = MAX(lsbp, 5);
while (cas == 0 && highcas >= lowcas) {
FOR_EACH_POPULATED_DIMM(s->dimms, i) {
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 4974173ef1..44e5d3a8ff 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
+#include <commonlib/helpers.h>
#include <console/console.h>
#include <string.h>
#include <arch/cpu.h>
@@ -1461,7 +1462,7 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank)
/* DRAM command ACT */
MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006;
MCHBAR32(0x4230 + 0x400 * channel) =
- (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10)
+ (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10)
| 4 | (ctrl->tRCD << 16);
MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | (6 << 16);
MCHBAR32(0x4210 + 0x400 * channel) = 0x244;
@@ -1499,7 +1500,7 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank)
/* DRAM command ACT */
MCHBAR32(0x4224 + 0x400 * channel) = 0x1f006;
MCHBAR32(0x4234 + 0x400 * channel) =
- (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10)
+ (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10)
| 8 | (ctrl->CAS << 16);
MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000;
MCHBAR32(0x4214 + 0x400 * channel) = 0x244;
@@ -1507,7 +1508,7 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank)
/* DRAM command RD */
MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;
MCHBAR32(0x4238 + 0x400 * channel) =
- 0x40011f4 | (max(ctrl->tRTP, 8) << 16);
+ 0x40011f4 | (MAX(ctrl->tRTP, 8) << 16);
MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24);
MCHBAR32(0x4218 + 0x400 * channel) = 0x242;
@@ -2101,7 +2102,7 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank)
/* DRAM command ACT */
MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006;
MCHBAR32(0x4230 + 0x400 * channel) =
- ((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10)
+ ((MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10)
| 8 | (ctrl->tRCD << 16);
MCHBAR32(0x4200 + 0x400 * channel) =
(slotrank << 24) | ctr | 0x60000;
@@ -2118,7 +2119,7 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank)
/* DRAM command RD */
MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;
MCHBAR32(0x4238 + 0x400 * channel) =
- 0x4001020 | (max(ctrl->tRTP, 8) << 16);
+ 0x4001020 | (MAX(ctrl->tRTP, 8) << 16);
MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24);
MCHBAR32(0x4248 + 0x400 * channel) = 0x389abcd;
MCHBAR32(0x4218 + 0x400 * channel) = 0x20e42;
@@ -2662,7 +2663,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel,
MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006;
MCHBAR32(0x4230 + 0x400 * channel) =
0x4 | (ctrl->tRCD << 16) |
- (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)
+ (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)
<< 10);
MCHBAR32(0x4200 + 0x400 * channel) =
(slotrank << 24) | 0x60000;
@@ -2679,7 +2680,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel,
/* DRAM command RD */
MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;
MCHBAR32(0x4238 + 0x400 * channel) =
- 0x4005020 | (max(ctrl->tRTP, 8) << 16);
+ 0x4005020 | (MAX(ctrl->tRTP, 8) << 16);
MCHBAR32(0x4208 + 0x400 * channel) =
slotrank << 24;
MCHBAR32(0x4218 + 0x400 * channel) = 0x242;
@@ -2717,9 +2718,9 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel,
rn.end, rn.start + ctrl->edge_offset[i],
rn.end - ctrl->edge_offset[i]);
lower[lane] =
- max(rn.start + ctrl->edge_offset[i], lower[lane]);
+ MAX(rn.start + ctrl->edge_offset[i], lower[lane]);
upper[lane] =
- min(rn.end - ctrl->edge_offset[i], upper[lane]);
+ MIN(rn.end - ctrl->edge_offset[i], upper[lane]);
edges[lane] = (lower[lane] + upper[lane]) / 2;
if (rn.all || (lower[lane] > upper[lane])) {
printk(BIOS_EMERG, "edge write discovery failed: %d, %d, %d\n",
@@ -2787,7 +2788,7 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank)
/* DRAM command ACT */
MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006;
MCHBAR32(0x4230 + 0x400 * channel) =
- (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD)
+ (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD)
<< 10) | (ctrl->tRCD << 16) | 4;
MCHBAR32(0x4200 + 0x400 * channel) =
(slotrank << 24) | 0x60000;
@@ -2803,7 +2804,7 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank)
/* DRAM command RD */
MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105;
MCHBAR32(0x4238 + 0x400 * channel) =
- 0x40011e0 | (max(ctrl->tRTP, 8) << 16);
+ 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16);
MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24;
MCHBAR32(0x4218 + 0x400 * channel) = 0x242;
@@ -2883,10 +2884,10 @@ int discover_timC_write(ramctr_timing *ctrl)
rn.start + ctrl->timC_offset[i],
rn.end - ctrl->timC_offset[i]);
lower[channel][slotrank][lane] =
- max(rn.start + ctrl->timC_offset[i],
+ MAX(rn.start + ctrl->timC_offset[i],
lower[channel][slotrank][lane]);
upper[channel][slotrank][lane] =
- min(rn.end - ctrl->timC_offset[i],
+ MIN(rn.end - ctrl->timC_offset[i],
upper[channel][slotrank][lane]);
}
@@ -2927,7 +2928,7 @@ void normalize_training(ramctr_timing * ctrl)
int delta;
mat = 0;
FOR_ALL_LANES mat =
- max(ctrl->timings[channel][slotrank].lanes[lane].timA, mat);
+ MAX(ctrl->timings[channel][slotrank].lanes[lane].timA, mat);
printram("normalize %d, %d, %d: mat %d\n",
channel, slotrank, lane, mat);
@@ -3080,8 +3081,8 @@ void set_4008c(ramctr_timing * ctrl)
int max_320c = -10000;
FOR_ALL_POPULATED_RANKS {
- max_320c = max(ctrl->timings[channel][slotrank].val_320c, max_320c);
- min_320c = min(ctrl->timings[channel][slotrank].val_320c, min_320c);
+ max_320c = MAX(ctrl->timings[channel][slotrank].val_320c, max_320c);
+ min_320c = MIN(ctrl->timings[channel][slotrank].val_320c, min_320c);
}
if (max_320c - min_320c > 51)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 01:36:12 +0000