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-rw-r--r--src/northbridge/intel/gm45/memmap.c16
-rw-r--r--src/northbridge/intel/i945/memmap.c16
-rw-r--r--src/northbridge/intel/nehalem/memmap.c17
-rw-r--r--src/northbridge/intel/pineview/memmap.c16
-rw-r--r--src/northbridge/intel/sandybridge/memmap.c15
-rw-r--r--src/northbridge/intel/x4x/memmap.c16
6 files changed, 37 insertions, 59 deletions
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 6e2f7037c2..7479a7834a 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -23,9 +23,9 @@
#include <device/pci_def.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
#include <cbmem.h>
#include <program_loading.h>
-#include <stage_cache.h>
#include <cpu/intel/smm_reloc.h>
#include "gm45.h"
@@ -84,7 +84,7 @@ u32 decode_tseg_size(u8 esmramc)
}
}
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
{
const pci_devfn_t dev = PCI_DEV(0, 0, 0);
@@ -107,7 +107,7 @@ u32 northbridge_get_tseg_base(void)
return tor;
}
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
{
const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
return decode_tseg_size(esmramc) << 10;
@@ -123,14 +123,10 @@ void *cbmem_top(void)
return (void *) top_of_ram;
}
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
- /* The stage cache lives at the end of the TSEG region.
- * The top of RAM is defined to be the TSEG base address.
- */
- *size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)((uintptr_t)northbridge_get_tseg_base()
- + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
+ *start = northbridge_get_tseg_base();
+ *size = northbridge_get_tseg_size();
}
void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index 8179f17888..8207d06a55 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -22,10 +22,10 @@
#include "i945.h"
#include <console/console.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
#include <program_loading.h>
#include <cpu/intel/smm_reloc.h>
#include <stdint.h>
-#include <stage_cache.h>
/* Decodes TSEG region size to bytes. */
u32 decode_tseg_size(const u8 esmramc)
@@ -45,7 +45,7 @@ u32 decode_tseg_size(const u8 esmramc)
}
}
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
{
uintptr_t tom;
@@ -60,7 +60,7 @@ u32 northbridge_get_tseg_base(void)
return tom;
}
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
{
const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
return decode_tseg_size(esmramc);
@@ -89,14 +89,10 @@ u32 decode_igd_memory_size(const u32 gms)
return ggc2uma[gms] << 10;
}
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
- /* The stage cache lives at the end of the TSEG region.
- * The top of RAM is defined to be the TSEG base address.
- */
- *size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)((uintptr_t)northbridge_get_tseg_base()
- + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
+ *start = northbridge_get_tseg_base();
+ *size = northbridge_get_tseg_size();
}
void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c
index 1687ddf78b..fd10542832 100644
--- a/src/northbridge/intel/nehalem/memmap.c
+++ b/src/northbridge/intel/nehalem/memmap.c
@@ -21,8 +21,8 @@
#include <cbmem.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
#include <program_loading.h>
-#include <stage_cache.h>
#include <cpu/intel/smm_reloc.h>
#include "nehalem.h"
@@ -33,12 +33,12 @@ static uintptr_t smm_region_start(void)
return tom;
}
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
{
- return (u32)smm_region_start();
+ return smm_region_start();
}
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
{
return CONFIG_SMM_TSEG_SIZE;
}
@@ -48,13 +48,10 @@ void *cbmem_top(void)
return (void *) smm_region_start();
}
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
- /* The stage cache lives at the end of TSEG region.
- * The top of RAM is defined to be the TSEG base address. */
- *size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)((uintptr_t)northbridge_get_tseg_base() +
- northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
+ *start = northbridge_get_tseg_base();
+ *size = northbridge_get_tseg_size();
}
void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index 9908f110cd..b4fef6bc76 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -24,9 +24,9 @@
#include <cbmem.h>
#include <northbridge/intel/pineview/pineview.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
#include <cpu/intel/smm_reloc.h>
#include <stdint.h>
-#include <stage_cache.h>
u8 decode_pciebar(u32 *const base, u32 *const len)
{
@@ -116,13 +116,13 @@ static u32 decode_tseg_size(const u32 esmramc)
}
}
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
{
const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
return decode_tseg_size(esmramc);
}
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
{
return pci_read_config32(PCI_DEV(0, 0, 0), TSEG);
}
@@ -139,14 +139,10 @@ void *cbmem_top(void)
}
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
- /* The stage cache lives at the end of the TSEG region.
- * The top of RAM is defined to be the TSEG base address.
- */
- *size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)((uintptr_t)northbridge_get_tseg_base()
- + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
+ *start = northbridge_get_tseg_base();
+ *size = northbridge_get_tseg_size();
}
void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index fa29b3782b..95bf4584ed 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -21,8 +21,8 @@
#include <console/console.h>
#include <cpu/intel/smm_reloc.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
#include <program_loading.h>
-#include <stage_cache.h>
#include "sandybridge.h"
static uintptr_t smm_region_start(void)
@@ -37,23 +37,20 @@ void *cbmem_top(void)
return (void *) smm_region_start();
}
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
{
return ALIGN_DOWN(smm_region_start(), 1*MiB);
}
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
{
return CONFIG_SMM_TSEG_SIZE;
}
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
- /* The stage cache lives at the end of TSEG region.
- * The top of RAM is defined to be the TSEG base address. */
- *size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)((uintptr_t)northbridge_get_tseg_base() + northbridge_get_tseg_size()
- - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE);
+ *start = northbridge_get_tseg_base();
+ *size = northbridge_get_tseg_size();
}
void fill_postcar_frame(struct postcar_frame *pcf)
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index 2f50768c46..41e491200b 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -25,10 +25,10 @@
#include <device/pci_def.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
#include <northbridge/intel/x4x/x4x.h>
#include <program_loading.h>
#include <cpu/intel/smm_reloc.h>
-#include <stage_cache.h>
/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
u32 decode_igd_memory_size(const u32 gms)
@@ -112,13 +112,13 @@ u8 decode_pciebar(u32 *const base, u32 *const len)
return 1;
}
-u32 northbridge_get_tseg_size(void)
+static size_t northbridge_get_tseg_size(void)
{
const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
return decode_tseg_size(esmramc);
}
-u32 northbridge_get_tseg_base(void)
+static uintptr_t northbridge_get_tseg_base(void)
{
return pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG);
}
@@ -134,14 +134,10 @@ void *cbmem_top(void)
return (void *) top_of_ram;
}
-void stage_cache_external_region(void **base, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
{
- /* The stage cache lives at the end of the TSEG region.
- * The top of RAM is defined to be the TSEG base address.
- */
- *size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)((uintptr_t)northbridge_get_tseg_base()
- + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
+ *start = northbridge_get_tseg_base();
+ *size = northbridge_get_tseg_size();
}
void fill_postcar_frame(struct postcar_frame *pcf)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 14:43:23 +0000