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-rw-r--r--src/northbridge/intel/e7501/debug.c42
-rw-r--r--src/northbridge/intel/e7501/raminit.c64
-rw-r--r--src/northbridge/intel/e7520/memory_initialized.c2
-rw-r--r--src/northbridge/intel/e7520/raminit.c42
-rw-r--r--src/northbridge/intel/e7525/raminit.c42
-rw-r--r--src/northbridge/intel/i3100/raminit.c32
-rw-r--r--src/northbridge/intel/i3100/raminit_ep80579.c122
-rw-r--r--src/northbridge/intel/i440bx/debug.c8
-rw-r--r--src/northbridge/intel/i440bx/raminit.c60
-rw-r--r--src/northbridge/intel/i440lx/raminit.c38
-rw-r--r--src/northbridge/intel/i82810/debug.c8
-rw-r--r--src/northbridge/intel/i82810/raminit.c34
-rw-r--r--src/northbridge/intel/i82830/raminit.c88
-rw-r--r--src/northbridge/intel/i855/debug.c28
-rw-r--r--src/northbridge/intel/i855/raminit.c28
15 files changed, 319 insertions, 319 deletions
diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c
index c05059be99..e5d3ac8741 100644
--- a/src/northbridge/intel/e7501/debug.c
+++ b/src/northbridge/intel/e7501/debug.c
@@ -27,7 +27,7 @@ static void print_pci_devices(void)
continue;
}
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
}
}
@@ -40,9 +40,9 @@ static void dump_pci_device(unsigned dev)
unsigned char val;
if ((i & 0x0f) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "\r\n%02x:",i);
+ printk(BIOS_DEBUG, "\n%02x:",i);
#else
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(i);
print_debug_char(':');
#endif
@@ -55,7 +55,7 @@ static void dump_pci_device(unsigned dev)
print_debug_hex8(val);
#endif
}
- print_debug("\r\n");
+ print_debug("\n");
}
static void dump_pci_devices(void)
@@ -95,7 +95,7 @@ static void dump_pci_devices_on_bus(unsigned busn)
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
@@ -114,9 +114,9 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
unsigned char byte;
if ((j & 0xf) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "\r\n%02x: ", j);
+ printk(BIOS_DEBUG, "\n%02x: ", j);
#else
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
#endif
@@ -133,7 +133,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
print_debug_char(' ');
#endif
}
- print_debug("\r\n");
+ print_debug("\n");
}
device = ctrl->channel1[i];
if (device) {
@@ -151,9 +151,9 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
unsigned char byte;
if ((j & 0xf) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "\r\n%02x: ", j);
+ printk(BIOS_DEBUG, "\n%02x: ", j);
#else
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
#endif
@@ -170,14 +170,14 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
print_debug_char(' ');
#endif
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
static void dump_smbus_registers(void)
{
unsigned device;
- print_debug("\r\n");
+ print_debug("\n");
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
@@ -196,9 +196,9 @@ static void dump_smbus_registers(void)
}
if ((j & 0xf) == 0) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "\r\n%02x: ",j);
+ printk(BIOS_DEBUG, "\n%02x: ",j);
#else
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
#endif
@@ -211,7 +211,7 @@ static void dump_smbus_registers(void)
print_debug_char(' ');
#endif
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
@@ -220,10 +220,10 @@ static void dump_io_resources(unsigned port)
int i;
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "%04x:\r\n", port);
+ printk(BIOS_DEBUG, "%04x:\n", port);
#else
print_debug_hex16(port);
- print_debug(":\r\n");
+ print_debug(":\n");
#endif
for(i=0;i<256;i++) {
uint8_t val;
@@ -243,7 +243,7 @@ static void dump_io_resources(unsigned port)
print_debug_hex8(val);
#endif
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
port++;
}
@@ -256,9 +256,9 @@ static void dump_mem(unsigned start, unsigned end)
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "\r\n%08x:", i);
+ printk(BIOS_DEBUG, "\n%08x:", i);
#else
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex32(i);
print_debug(":");
#endif
@@ -270,6 +270,6 @@ static void dump_mem(unsigned start, unsigned end)
print_debug_hex8((unsigned char)*((unsigned char *)i));
#endif
}
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c
index c1866070ff..70a692cd92 100644
--- a/src/northbridge/intel/e7501/raminit.c
+++ b/src/northbridge/intel/e7501/raminit.c
@@ -35,7 +35,7 @@
#endif
#define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4)
-#define SPD_ERROR "Error reading SPD info\r\n"
+#define SPD_ERROR "Error reading SPD info\n"
// NOTE: This used to be 0x100000.
// That doesn't work on systems where A20M# is asserted, because
@@ -481,7 +481,7 @@ static void do_delay(void)
static void die_on_spd_error(int spd_return_value)
{
if (spd_return_value < 0)
- die("Error reading SPD info\r\n");
+ die("Error reading SPD info\n");
}
//----------------------------------------------------------------------------------
@@ -522,7 +522,7 @@ static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
if (value < 0) goto hw_err;
if (value > 2)
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
if (value == 2) {
pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently
@@ -755,7 +755,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
spd_value = spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
+ print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
continue;
}
@@ -780,11 +780,11 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
dimm_mask |= ((1<<i) | (1<<(MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
}
else
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
+ print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
#else
switch (bDualChannel) {
case 0:
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
+ print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
break;
default:
@@ -873,7 +873,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
RAM_DEBUG_MESSAGE(" Sending RAM command to 0x");
RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits);
- RAM_DEBUG_MESSAGE("\r\n");
+ RAM_DEBUG_MESSAGE("\n");
read32(dimm_start_address + e7501_mode_bits);
// Set the start of the next DIMM
@@ -1017,10 +1017,10 @@ static void configure_e7501_ram_addresses(const struct mem_controller *ctrl,
RAM_DEBUG_HEX32(sz.side1);
RAM_DEBUG_MESSAGE(" ");
RAM_DEBUG_HEX32(sz.side2);
- RAM_DEBUG_MESSAGE("\r\n");
+ RAM_DEBUG_MESSAGE("\n");
if (sz.side1 == 0)
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
total_dram_64M_multiple = configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i);
}
@@ -1105,7 +1105,7 @@ static void initialize_ecc(void)
uint8_t byte;
- RAM_DEBUG_MESSAGE("Initializing ECC state...\r\n");
+ RAM_DEBUG_MESSAGE("Initializing ECC state...\n");
/* Initialize ECC bits , use ECC zero mode (new to 7501)*/
pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x06);
pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x07);
@@ -1117,7 +1117,7 @@ static void initialize_ecc(void)
} while ( (byte & 0x08 ) == 0);
pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc);
- RAM_DEBUG_MESSAGE("ECC state initialized.\r\n");
+ RAM_DEBUG_MESSAGE("ECC state initialized.\n");
/* Clear the ECC error bits */
pci_write_config8(PCI_DEV(0, 0, 1), DRAM_FERR, 0x03);
@@ -1373,7 +1373,7 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, uint8
}
}
else
- die("No CAS# latencies compatible with all DIMMs!!\r\n");
+ die("No CAS# latencies compatible with all DIMMs!!\n");
pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
@@ -1462,14 +1462,14 @@ static void configure_e7501_dram_controller_mode(const struct mem_controller *ct
die_on_spd_error(value);
value &= 0x7f; // Mask off self-refresh bit
if(value > MAX_SPD_REFRESH_RATE) {
- print_err("unsupported refresh rate\r\n");
+ print_err("unsupported refresh rate\n");
continue;
}
// Get the appropriate E7501 refresh mode for this DIMM
dimm_refresh_mode = refresh_rate_map[value];
if (dimm_refresh_mode > 7) {
- print_err("unsupported refresh rate\r\n");
+ print_err("unsupported refresh rate\n");
continue;
}
@@ -1680,7 +1680,7 @@ static void ram_set_rcomp_regs(void)
uint32_t dword;
uint8_t maybe_strength_control;
- RAM_DEBUG_MESSAGE("Setting RCOMP registers.\r\n");
+ RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
/*enable access to the rcomp bar*/
dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
@@ -1805,8 +1805,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
return;
/* 1 & 2 Power up and start clocks */
- RAM_DEBUG_MESSAGE("Ram Enable 1\r\n");
- RAM_DEBUG_MESSAGE("Ram Enable 2\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 1\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 2\n");
/* A 200us delay is needed */
@@ -1814,23 +1814,23 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
EXTRA_DELAY
/* 3. Apply NOP */
- RAM_DEBUG_MESSAGE("Ram Enable 3\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 3\n");
do_ram_command(RAM_COMMAND_NOP, 0);
EXTRA_DELAY
/* 4 Precharge all */
- RAM_DEBUG_MESSAGE("Ram Enable 4\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 4\n");
do_ram_command(RAM_COMMAND_PRECHARGE, 0);
EXTRA_DELAY
/* wait until the all banks idle state... */
/* 5. Issue EMRS to enable DLL */
- RAM_DEBUG_MESSAGE("Ram Enable 5\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 5\n");
do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL);
EXTRA_DELAY
/* 6. Reset DLL */
- RAM_DEBUG_MESSAGE("Ram Enable 6\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 6\n");
set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);
EXTRA_DELAY
@@ -1842,12 +1842,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
EXTRA_DELAY
/* 7 Precharge all */
- RAM_DEBUG_MESSAGE("Ram Enable 7\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 7\n");
do_ram_command(RAM_COMMAND_PRECHARGE, 0);
EXTRA_DELAY
/* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
- RAM_DEBUG_MESSAGE("Ram Enable 8\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 8\n");
do_ram_command(RAM_COMMAND_CBR, 0);
EXTRA_DELAY
do_ram_command(RAM_COMMAND_CBR, 0);
@@ -1867,17 +1867,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
EXTRA_DELAY
/* 9 mode register set */
- RAM_DEBUG_MESSAGE("Ram Enable 9\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 9\n");
set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);
EXTRA_DELAY
/* 10 DDR Receive FIFO RE-Sync */
- RAM_DEBUG_MESSAGE("Ram Enable 10\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 10\n");
RAM_RESET_DDR_PTR();
EXTRA_DELAY
/* 11 normal operation */
- RAM_DEBUG_MESSAGE("Ram Enable 11\r\n");
+ RAM_DEBUG_MESSAGE("Ram Enable 11\n");
do_ram_command(RAM_COMMAND_NORMAL, 0);
EXTRA_DELAY
@@ -1897,7 +1897,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
dram_controller_mode |= (1<<17); // NOTE: undocumented reserved bit
pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
- RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\r\n");
+ RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n");
DUMPNORTH();
// verify_ram();
@@ -1917,19 +1917,19 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
uint8_t dimm_mask;
- RAM_DEBUG_MESSAGE("Reading SPD data...\r\n");
+ RAM_DEBUG_MESSAGE("Reading SPD data...\n");
//activate_spd_rom(ctrl); Not necessary for this chipset
dimm_mask = spd_get_supported_dimms(ctrl);
if (dimm_mask == 0) {
- print_debug("No usable memory for this controller\r\n");
+ print_debug("No usable memory for this controller\n");
} else {
enable_e7501_clocks(dimm_mask);
- RAM_DEBUG_MESSAGE("setting based on SPD data...\r\n");
+ RAM_DEBUG_MESSAGE("setting based on SPD data...\n");
configure_e7501_row_attributes(ctrl, dimm_mask);
configure_e7501_dram_controller_mode(ctrl, dimm_mask);
@@ -1938,7 +1938,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
configure_e7501_dram_timing(ctrl, dimm_mask);
DO_DELAY
- RAM_DEBUG_MESSAGE("done\r\n");
+ RAM_DEBUG_MESSAGE("done\n");
}
// NOTE: configure_e7501_ram_addresses() is NOT called here.
@@ -1963,7 +1963,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
//
static void sdram_set_registers(const struct mem_controller *ctrl)
{
- RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\r\n");
+ RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n");
DUMPNORTH();
ram_set_rcomp_regs();
diff --git a/src/northbridge/intel/e7520/memory_initialized.c b/src/northbridge/intel/e7520/memory_initialized.c
index 3b9b696a21..133d1c4f88 100644
--- a/src/northbridge/intel/e7520/memory_initialized.c
+++ b/src/northbridge/intel/e7520/memory_initialized.c
@@ -7,7 +7,7 @@ static inline int memory_initialized(void)
drc = pci_read_config32(NB_DEV, DRC);
//print_debug("memory_initialized: DRC: ");
//print_debug_hex32(drc);
- //print_debug("\r\n");
+ //print_debug("\n");
return (drc & (1<<29));
}
diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index 3965addcb2..836e6f8c7c 100644
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -74,7 +74,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
- print_spew("done.\r\n");
+ print_spew("done.\n");
}
@@ -155,7 +155,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
sz.side1 = 0;
@@ -283,7 +283,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
dra = 0;
@@ -538,7 +538,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
}
else {
- die("Invalid SPD 9 bus speed.\r\n");
+ die("Invalid SPD 9 bus speed.\n");
}
/* 0x78 DRT */
@@ -576,7 +576,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
ecc = 2;
}
else if (ecc == 1) {
- die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+ die("ERROR - Mixed DDR & DDR2 RAM\n");
}
}
else if ( reg == 7 ) {
@@ -584,15 +584,15 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
ecc = 1;
}
else if ( ecc > 1 ) {
- die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+ die("ERROR - Mixed DDR & DDR2 RAM\n");
}
}
else {
- die("ERROR - RAM not DDR\r\n");
+ die("ERROR - RAM not DDR\n");
}
}
else {
- die("ERROR - Non ECC memory dimm\r\n");
+ die("ERROR - Non ECC memory dimm\n");
}
value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
@@ -621,10 +621,10 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
ecc = 2;
if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
ecc = 0; /* ECC off in CMOS so disable it */
- print_debug("ECC off\r\n");
+ print_debug("ECC off\n");
}
else {
- print_debug("ECC on\r\n");
+ print_debug("ECC on\n");
}
drc &= ~(3 << 20); /* clear the ecc bits */
drc |= (ecc << 20); /* or in the calculated ecc bits */
@@ -654,7 +654,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
drc = 0;
@@ -669,7 +669,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
/* Test if we can read the spd and if ram is ddr or ddr2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\r\n");
+ print_err("No memory for this cpu\n");
return;
}
return;
@@ -771,12 +771,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
data32 = 0x777becdc; /* ESSD */
break;
}
- die("Error - First dimm slot empty\r\n");
+ die("Error - First dimm slot empty\n");
}
print_debug("ODT Value = ");
print_debug_hex32(data32);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(PCI_DEV(0, 0x00, 0), 0xb0, data32);
@@ -1009,7 +1009,7 @@ static void set_receive_enable(const struct mem_controller *ctrl)
print_debug_hex32(recena);
print_debug(", Receive enable B = ");
print_debug_hex32(recenb);
- print_debug("\r\n");
+ print_debug("\n");
/* clear out the calibration area */
write32(BAR+DCALDATA+(16*4), 0x00000000);
@@ -1075,7 +1075,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
0xffffffff, 0xffffffff, 0x000000ff};
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\r\n");
+ print_debug("Starting SDRAM Enable\n");
/* 0x80 */
#ifdef DIMM_MAP_LOGICAL
@@ -1087,7 +1087,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
if( drc == 0) {
- die("Error calculating DRC\r\n");
+ die("Error calculating DRC\n");
}
pll_setup(drc);
data32 = drc & ~(3 << 20); /* clear ECC mode */
@@ -1124,7 +1124,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for(i=0;i<8;i++) { /* loop throught each dimm to test for row */
print_debug("DIMM ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
/* Apply NOP */
do_delay();
@@ -1307,7 +1307,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
write32(BAR+DCALCSR, 0x0008000f);
/* clear memory and init ECC */
- print_debug("Clearing memory\r\n");
+ print_debug("Clearing memory\n");
for(i=0;i<64;i+=4) {
write32(BAR+DCALDATA+i, 0x00000000);
}
@@ -1324,13 +1324,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
data32 |= (1 << 31);
pci_write_config32(PCI_DEV(0, 0x00, 0), 0x98, data32);
/* wait for completion */
- print_debug("Waiting for mem complete\r\n");
+ print_debug("Waiting for mem complete\n");
while(1) {
data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98);
if( (data32 & (1<<31)) == 0)
break;
}
- print_debug("Done\r\n");
+ print_debug("Done\n");
/* Set initialization complete */
/* 0x7c DRC */
diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index 4aaa26480d..0d18022020 100644
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -74,7 +74,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
- print_spew("done.\r\n");
+ print_spew("done.\n");
}
@@ -155,7 +155,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
sz.side1 = 0;
@@ -283,7 +283,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
dra = 0;
@@ -538,7 +538,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
}
else {
- die("Invalid SPD 9 bus speed.\r\n");
+ die("Invalid SPD 9 bus speed.\n");
}
/* 0x78 DRT */
@@ -576,7 +576,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
ecc = 2;
}
else if (ecc == 1) {
- die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+ die("ERROR - Mixed DDR & DDR2 RAM\n");
}
}
else if ( reg == 7 ) {
@@ -584,15 +584,15 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
ecc = 1;
}
else if ( ecc > 1 ) {
- die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+ die("ERROR - Mixed DDR & DDR2 RAM\n");
}
}
else {
- die("ERROR - RAM not DDR\r\n");
+ die("ERROR - RAM not DDR\n");
}
}
else {
- die("ERROR - Non ECC memory dimm\r\n");
+ die("ERROR - Non ECC memory dimm\n");
}
value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
@@ -621,10 +621,10 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
ecc = 2;
if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
ecc = 0; /* ECC off in CMOS so disable it */
- print_debug("ECC off\r\n");
+ print_debug("ECC off\n");
}
else {
- print_debug("ECC on\r\n");
+ print_debug("ECC on\n");
}
drc &= ~(3 << 20); /* clear the ecc bits */
drc |= (ecc << 20); /* or in the calculated ecc bits */
@@ -654,7 +654,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
drc = 0;
@@ -669,7 +669,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
/* Test if we can read the spd and if ram is ddr or ddr2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\r\n");
+ print_err("No memory for this cpu\n");
return;
}
return;
@@ -742,12 +742,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
data32 = 0x777becdc; /* ESSD */
break;
}
- die("Error - First dimm slot empty\r\n");
+ die("Error - First dimm slot empty\n");
}
print_debug("ODT Value = ");
print_debug_hex32(data32);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, 0xb0, data32);
@@ -980,7 +980,7 @@ static void set_receive_enable(const struct mem_controller *ctrl)
print_debug_hex32(recena);
print_debug(", Receive enable B = ");
print_debug_hex32(recenb);
- print_debug("\r\n");
+ print_debug("\n");
/* clear out the calibration area */
write32(BAR+DCALDATA+(16*4), 0x00000000);
@@ -1046,7 +1046,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
0xffffffff, 0xffffffff, 0x000000ff};
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\r\n");
+ print_debug("Starting SDRAM Enable\n");
/* 0x80 */
#ifdef DIMM_MAP_LOGICAL
@@ -1058,7 +1058,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
if( drc == 0) {
- die("Error calculating DRC\r\n");
+ die("Error calculating DRC\n");
}
data32 = drc & ~(3 << 20); /* clear ECC mode */
data32 = data32 & ~(7 << 8); /* clear refresh rates */
@@ -1094,7 +1094,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for(i=0;i<8;i++) { /* loop throught each dimm to test for row */
print_debug("DIMM ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
/* Apply NOP */
do_delay();
@@ -1274,7 +1274,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
write32(BAR+DCALCSR, 0x0008000f);
/* clear memory and init ECC */
- print_debug("Clearing memory\r\n");
+ print_debug("Clearing memory\n");
for(i=0;i<64;i+=4) {
write32(BAR+DCALDATA+i, 0x00000000);
}
@@ -1291,13 +1291,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
data32 |= (1 << 31);
pci_write_config32(ctrl->f0, 0x98, data32);
/* wait for completion */
- print_debug("Waiting for mem complete\r\n");
+ print_debug("Waiting for mem complete\n");
while(1) {
data32 = pci_read_config32(ctrl->f0, 0x98);
if( (data32 & (1<<31)) == 0)
break;
}
- print_debug("Done\r\n");
+ print_debug("Done\n");
/* Set initialization complete */
/* 0x7c DRC */
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 76475ce235..fa44d599f1 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -76,7 +76,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
- print_spew("done.\r\n");
+ print_spew("done.\n");
}
struct dimm_size {
@@ -149,7 +149,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
sz.side1 = 0;
@@ -277,7 +277,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
dra = 0;
@@ -528,7 +528,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
}
else {
- die("Invalid SPD 9 bus speed.\r\n");
+ die("Invalid SPD 9 bus speed.\n");
}
/* 0x78 DRT */
@@ -556,7 +556,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
continue;
}
value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */
- if (value != 2) die("ERROR - Non ECC memory dimm\r\n");
+ if (value != 2) die("ERROR - Non ECC memory dimm\n");
value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
value &= 0x0f; /* clip self refresh bit */
@@ -595,7 +595,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
drc = 0;
@@ -610,7 +610,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
/* Test if we can read the spd and if ram is ddr or ddr2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\r\n");
+ print_err("No memory for this cpu\n");
return;
}
return;
@@ -683,12 +683,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
data32 = 0x777becdc; /* ESSD */
break;
}
- die("Error - First dimm slot empty\r\n");
+ die("Error - First dimm slot empty\n");
}
print_debug("ODT Value = ");
print_debug_hex32(data32);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, DDR2ODTC, data32);
@@ -921,7 +921,7 @@ static void set_receive_enable(const struct mem_controller *ctrl)
print_debug_hex32(recena);
print_debug(", Receive enable B = ");
print_debug_hex32(recenb);
- print_debug("\r\n");
+ print_debug("\n");
/* clear out the calibration area */
write32(MCBAR+DCALDATA+(16*4), 0x00000000);
@@ -977,7 +977,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
0xffffffff, 0xffffffff, 0x000000ff};
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\r\n");
+ print_debug("Starting SDRAM Enable\n");
/* 0x80 */
#ifdef DIMM_MAP_LOGICAL
@@ -989,7 +989,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
if( drc == 0) {
- die("Error calculating DRC\r\n");
+ die("Error calculating DRC\n");
}
data32 = drc & ~(3 << 20); /* clear ECC mode */
data32 = data32 & ~(7 << 8); /* clear refresh rates */
@@ -1024,7 +1024,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for(i=0;i<8;i+=2) { /* loop through each dimm to test */
print_debug("DIMM ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
/* Apply NOP */
do_delay();
@@ -1177,7 +1177,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
write32(MCBAR+DCALCSR, 0x0008000f);
/* clear memory and init ECC */
- print_debug("Clearing memory\r\n");
+ print_debug("Clearing memory\n");
for(i=0;i<64;i+=4) {
write32(MCBAR+DCALDATA+i, 0x00000000);
}
@@ -1194,13 +1194,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
data32 |= (1 << 31);
pci_write_config32(ctrl->f0, 0x98, data32);
/* wait for completion */
- print_debug("Waiting for mem complete\r\n");
+ print_debug("Waiting for mem complete\n");
while(1) {
data32 = pci_read_config32(ctrl->f0, 0x98);
if( (data32 & (1<<31)) == 0)
break;
}
- print_debug("Done\r\n");
+ print_debug("Done\n");
/* Set initialization complete */
/* 0x7c DRC */
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 9ad778bf13..5a4a328e44 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -122,7 +122,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
sz.side1 = 0;
@@ -134,7 +134,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
print_debug_hex8(sz.side1);
print_debug(".");
print_debug_hex8(sz.side2);
- print_debug("\r\n");
+ print_debug("\n");
return sz;
}
@@ -167,14 +167,14 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, u8 dimm_mask)
}
print_debug("DRB = ");
print_debug_hex32(pci_read_config32(ctrl->f0, DRB));
- print_debug("\r\n");
+ print_debug("\n");
cum >>= 1;
/* set TOM top of memory */
pci_write_config16(ctrl->f0, TOM, cum);
print_debug("TOM = ");
print_debug_hex16(cum);
- print_debug("\r\n");
+ print_debug("\n");
/* set TOLM top of low memory */
if (cum > 0x18) {
cum = 0x18;
@@ -183,7 +183,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, u8 dimm_mask)
pci_write_config16(ctrl->f0, TOLM, cum);
print_debug("TOLM = ");
print_debug_hex16(cum);
- print_debug("\r\n");
+ print_debug("\n");
return 0;
}
@@ -202,7 +202,7 @@ static u8 spd_detect_dimms(const struct mem_controller *ctrl)
print_debug_hex8(device);
print_debug(" = ");
print_debug_hex8(byte);
- print_debug("\r\n");
+ print_debug("\n");
if (byte == 8) {
dimm_mask |= (1 << i);
}
@@ -227,29 +227,29 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
}
value = spd_read_byte(ctrl->channel0[i], SPD_NUM_ROWS);
- if (value < 0) die("Bad SPD data\r\n");
- if ((value & 0xf) == 0) die("Invalid # of rows\r\n");
+ if (value < 0) die("Bad SPD data\n");
+ if ((value & 0xf) == 0) die("Invalid # of rows\n");
dra |= (((value-13) & 0x7) << 23);
dra |= (((value-13) & 0x7) << 29);
reg += value & 0xf;
value = spd_read_byte(ctrl->channel0[i], SPD_NUM_COLUMNS);
- if (value < 0) die("Bad SPD data\r\n");
- if ((value & 0xf) == 0) die("Invalid # of columns\r\n");
+ if (value < 0) die("Bad SPD data\n");
+ if ((value & 0xf) == 0) die("Invalid # of columns\n");
dra |= (((value-10) & 0x7) << 20);
dra |= (((value-10) & 0x7) << 26);
reg += value & 0xf;
value = spd_read_byte(ctrl->channel0[i], SPD_NUM_BANKS_PER_SDRAM);
- if (value < 0) die("Bad SPD data\r\n");
- if ((value & 0xff) == 0) die("Invalid # of banks\r\n");
+ if (value < 0) die("Bad SPD data\n");
+ if ((value & 0xff) == 0) die("Invalid # of banks\n");
reg += log2(value & 0xff);
print_debug("dimm ");
print_debug_hex8(i);
print_debug(" reg = ");
print_debug_hex8(reg);
- print_debug("\r\n");
+ print_debug("\n");
/* set device density */
dra |= ((31-reg));
@@ -270,7 +270,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
print_debug_hex8(i);
print_debug(" = ");
print_debug_hex32(dra);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, DRA + (i*4), dra);
}
@@ -320,10 +320,10 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
else if (val & 0x40)
cl = 6;
else
- die("CAS latency mismatch\r\n");
+ die("CAS latency mismatch\n");
print_debug("cl = ");
print_debug_hex8(cl);
- print_debug("\r\n");
+ print_debug("\n");
ci = cycle[index];
@@ -349,10 +349,10 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
}
print_debug("trc = ");
print_debug_hex8(trc);
- print_debug("\r\n");
+ print_debug("\n");
print_debug("trfc = ");
print_debug_hex8(trfc);
- print_debug("\r\n");
+ print_debug("\n");
/* Tras, Trtp, Twtr in cycles */
for (i = 0; i < DIMM_SOCKETS; i++) {
@@ -374,38 +374,38 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
}
print_debug("tras = ");
print_debug_hex8(tras);
- print_debug("\r\n");
+ print_debug("\n");
print_debug("trtp = ");
print_debug_hex8(trtp);
- print_debug("\r\n");
+ print_debug("\n");
print_debug("twtr = ");
print_debug_hex8(twtr);
- print_debug("\r\n");
+ print_debug("\n");
val = (drt0[index] | ((trc - 11) << 12) | ((cl - 3) << 9)
| ((cl - 3) << 6) | ((cl - 3) << 3));
print_debug("drt0 = ");
print_debug_hex32(val);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, DRT0, val);
val = (drt1[index] | ((tras - 8) << 28) | ((trtp - 2) << 25)
| (twtr << 15));
print_debug("drt1 = ");
print_debug_hex32(val);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, DRT1, val);
val = (magic[index]);
print_debug("magic = ");
print_debug_hex32(val);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(PCI_DEV(0, 0x08, 0), 0xcc, val);
val = (mrs[index] | (cl << 20));
print_debug("mrs = ");
print_debug_hex32(val);
- print_debug("\r\n");
+ print_debug("\n");
return val;
}
@@ -422,11 +422,11 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
if (!(dimm_mask & (1 << i)))
continue;
if ((spd_read_byte(ctrl->channel0[i], SPD_MODULE_DATA_WIDTH_LSB) & 0xf0) != 0x40)
- die("ERROR: Only 64-bit DIMMs supported\r\n");
+ die("ERROR: Only 64-bit DIMMs supported\n");
if (!(spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONFIG_TYPE) & 0x02))
- die("ERROR: Only ECC DIMMs supported\r\n");
+ die("ERROR: Only ECC DIMMs supported\n");
if (spd_read_byte(ctrl->channel0[i], SPD_PRIMARY_SDRAM_WIDTH) != 0x08)
- die("ERROR: Only x8 DIMMs supported\r\n");
+ die("ERROR: Only x8 DIMMs supported\n");
value = spd_read_byte(ctrl->channel0[i], SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
if (value > cycle)
@@ -434,7 +434,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
}
print_debug("cycle = ");
print_debug_hex8(cycle);
- print_debug("\r\n");
+ print_debug("\n");
drc |= (1 << 20); /* enable ECC */
drc |= (3 << 30); /* enable CKE on each DIMM */
@@ -446,42 +446,42 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
print_debug("msr 0xcd = ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
- print_debug("\r\n");
+ print_debug("\n");
/* TODO check that this msr really indicates fsb speed! */
if (msr.lo & 0x07) {
- print_info("533 MHz FSB\r\n");
+ print_info("533 MHz FSB\n");
if (cycle <= 0x25) {
drc |= 0x5;
- print_info("400 MHz DDR\r\n");
+ print_info("400 MHz DDR\n");
} else if (cycle <= 0x30) {
drc |= 0x7;
- print_info("333 MHz DDR\r\n");
+ print_info("333 MHz DDR\n");
} else if (cycle <= 0x3d) {
drc |= 0x4;
- print_info("266 MHz DDR\r\n");
+ print_info("266 MHz DDR\n");
} else {
drc |= 0x2;
- print_info("200 MHz DDR\r\n");
+ print_info("200 MHz DDR\n");
}
}
else {
- print_info("400 MHz FSB\r\n");
+ print_info("400 MHz FSB\n");
if (cycle <= 0x30) {
drc |= 0x7;
- print_info("333 MHz DDR\r\n");
+ print_info("333 MHz DDR\n");
} else if (cycle <= 0x3d) {
drc |= 0x0;
- print_info("266 MHz DDR\r\n");
+ print_info("266 MHz DDR\n");
} else {
drc |= 0x2;
- print_info("200 MHz DDR\r\n");
+ print_info("200 MHz DDR\n");
}
}
print_debug("DRC = ");
print_debug_hex32(drc);
- print_debug("\r\n");
+ print_debug("\n");
return drc;
}
@@ -494,7 +494,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
/* Test if we can read the SPD */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\r\n");
+ print_err("No memory for this cpu\n");
return;
}
return;
@@ -524,14 +524,14 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
print_debug("ODT Value = ");
print_debug_hex32(data32);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, DDR2ODTC, data32);
for (i = 0; i < 2; i++) {
print_debug("ODT CS");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21));
@@ -547,14 +547,14 @@ static void dump_dcal_regs(void)
int i;
for (i = 0x0; i < 0x2a0; i += 4) {
if ((i % 16) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex16(i);
print_debug(": ");
}
print_debug_hex32(read32(BAR+i));
print_debug(" ");
}
- print_debug("\r\n");
+ print_debug("\n");
}
@@ -570,12 +570,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
u16 data16;
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\r\n");
+ print_debug("Starting SDRAM Enable\n");
/* Set DRAM type and Front Side Bus frequency */
drc = spd_set_dram_controller_mode(ctrl, mask);
if (drc == 0) {
- die("Error calculating DRC\r\n");
+ die("Error calculating DRC\n");
}
data32 = drc & ~(3 << 20); /* clear ECC mode */
data32 = data32 | (3 << 5); /* temp turn off ODT */
@@ -600,7 +600,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("NOP CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
udelay(16);
write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21)));
write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21)));
@@ -614,7 +614,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("NOP CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000)
@@ -626,7 +626,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("Precharge CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, 0x04000000);
write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
@@ -639,7 +639,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("EMRS CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
@@ -651,7 +651,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("MRS CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, mode_reg);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
@@ -664,7 +664,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("Precharge CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, 0x04000000);
write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
@@ -678,7 +678,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("Refresh CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000)
@@ -691,7 +691,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("MRS CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
@@ -704,7 +704,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
print_debug("EMRS CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
@@ -728,7 +728,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 1; cs++) {
print_debug("receive enable calibration CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21)));
data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000)
@@ -755,17 +755,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
continue;
print_debug("clear memory CS");
print_debug_hex8(cs);
- print_debug("\r\n");
+ print_debug("\n");
write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16));
data32 = read32(BAR+MBCSR);
while (data32 & 0x80000000)
data32 = read32(BAR+MBCSR);
if (data32 & 0x40000000)
- print_debug("failed!\r\n");
+ print_debug("failed!\n");
}
/* Clear read/write FIFO pointers */
- print_debug("clear read/write fifo pointers\r\n");
+ print_debug("clear read/write fifo pointers\n");
write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15));
udelay(16);
write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15));
@@ -773,7 +773,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
dump_dcal_regs();
- print_debug("Done\r\n");
+ print_debug("Done\n");
/* Set initialization complete */
drc |= (1 << 29);
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
index fab224dc85..b437755213 100644
--- a/src/northbridge/intel/i440bx/debug.c
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -2,7 +2,7 @@
static void dump_spd_registers(void)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < DIMM_SOCKETS; i++) {
unsigned device;
device = DIMM_SPD_BASE + i;
@@ -16,20 +16,20 @@ static void dump_spd_registers(void)
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = spd_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 016bf67f93..789ea82db9 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -420,7 +420,7 @@ static void do_ram_command(u32 command)
PRINT_DEBUG_HEX16(reg16);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
read32(addr);
@@ -606,7 +606,7 @@ static void spd_enable_refresh(void)
PRINT_DEBUG_HEX8(reg);
PRINT_DEBUG(") for DIMM ");
PRINT_DEBUG_HEX8(i);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
}
pci_write_config8(NB, DRAMC, reg);
@@ -621,7 +621,7 @@ static void sdram_set_registers(void)
int i, max;
uint8_t reg;
- PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge prior to SDRAM init:\n");
DUMPNORTH();
max = ARRAY_SIZE(register_values);
@@ -637,7 +637,7 @@ static void sdram_set_registers(void)
PRINT_DEBUG_HEX8(register_values[i]);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX8(reg);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
}
}
@@ -731,11 +731,11 @@ static void set_dram_row_attributes(void)
}
PRINT_DEBUG("DIMM in slot ");
PRINT_DEBUG_HEX8(i);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
if (edosd == 0x06) {
- print_err("Mixing EDO/SDRAM unsupported!\r\n");
- die("HALT\r\n");
+ print_err("Mixing EDO/SDRAM unsupported!\n");
+ die("HALT\n");
}
/* "DRA" is our RPS for the two rows on this DIMM. */
@@ -816,12 +816,12 @@ static void set_dram_row_attributes(void)
if (col == 4)
bpr |= 0xc0;
} else {
- print_err("# of banks of DIMM unsupported!\r\n");
- die("HALT\r\n");
+ print_err("# of banks of DIMM unsupported!\n");
+ die("HALT\n");
}
if (dra == -1) {
- print_err("Page size not supported\r\n");
- die("HALT\r\n");
+ print_err("Page size not supported\n");
+ die("HALT\n");
}
/*
@@ -831,14 +831,14 @@ static void set_dram_row_attributes(void)
*/
struct dimm_size sz = spd_get_dimm_size(device);
if ((sz.side1 < 8)) {
- print_err("DIMMs smaller than 8MB per side\r\n"
- "are not supported on this NB.\r\n");
- die("HALT\r\n");
+ print_err("DIMMs smaller than 8MB per side\n"
+ "are not supported on this NB.\n");
+ die("HALT\n");
}
if ((sz.side1 > 128)) {
- print_err("DIMMs > 128MB per side\r\n"
- "are not supported on this NB\r\n");
- die("HALT\r\n");
+ print_err("DIMMs > 128MB per side\n"
+ "are not supported on this NB\n");
+ die("HALT\n");
}
/* Divide size by 8 to set up the DRB registers. */
@@ -855,7 +855,7 @@ static void set_dram_row_attributes(void)
#if 0
PRINT_DEBUG("No DIMM found in slot ");
PRINT_DEBUG_HEX8(i);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
/* If there's no DIMM in the slot, set dra to 0x00. */
@@ -870,7 +870,7 @@ static void set_dram_row_attributes(void)
#if 0
PRINT_DEBUG("DRB has been set to 0x");
PRINT_DEBUG_HEX16(drb);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
/* Brings the upper DRB back down to be base for
@@ -886,19 +886,19 @@ static void set_dram_row_attributes(void)
pci_write_config8(NB, PGPOL + 1, bpr);
PRINT_DEBUG("PGPOL[BPR] has been set to 0x");
PRINT_DEBUG_HEX8(bpr);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/* Set DRAM row page size register. */
pci_write_config16(NB, RPS, rps);
PRINT_DEBUG("RPS has been set to 0x");
PRINT_DEBUG_HEX16(rps);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/* ### ECC */
pci_write_config8(NB, NBXCFG + 3, nbxecc);
PRINT_DEBUG("NBXECC[31:24] has been set to 0x");
PRINT_DEBUG_HEX8(nbxecc);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/* Set DRAMC[4:3] to proper memory type (EDO/SDRAM).
* TODO: Registered SDRAM support.
@@ -917,7 +917,7 @@ static void set_dram_row_attributes(void)
pci_write_config8(NB, DRAMC, value);
PRINT_DEBUG("DRAMC has been set to 0x");
PRINT_DEBUG_HEX8(value);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
}
static void sdram_set_spd_registers(void)
@@ -947,38 +947,38 @@ static void sdram_enable(void)
udelay(200);
/* 1. Apply NOP. Wait 200 clock cycles (200us should do). */
- PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
+ PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
do_ram_command(RAM_COMMAND_NOP);
udelay(200);
/* 2. Precharge all. Wait tRP. */
- PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
+ PRINT_DEBUG("RAM Enable 2: Precharge all\n");
do_ram_command(RAM_COMMAND_PRECHARGE);
udelay(1);
/* 3. Perform 8 refresh cycles. Wait tRC each time. */
- PRINT_DEBUG("RAM Enable 3: CBR\r\n");
+ PRINT_DEBUG("RAM Enable 3: CBR\n");
for (i = 0; i < 8; i++) {
do_ram_command(RAM_COMMAND_CBR);
udelay(1);
}
/* 4. Mode register set. Wait two memory cycles. */
- PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
+ PRINT_DEBUG("RAM Enable 4: Mode register set\n");
do_ram_command(RAM_COMMAND_MRS);
udelay(2);
/* 5. Normal operation. */
- PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
+ PRINT_DEBUG("RAM Enable 5: Normal operation\n");
do_ram_command(RAM_COMMAND_NORMAL);
udelay(1);
/* 6. Finally enable refresh. */
- PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n");
+ PRINT_DEBUG("RAM Enable 6: Enable refresh\n");
// pci_write_config8(NB, PMCR, 0x10);
spd_enable_refresh();
udelay(1);
- PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge following SDRAM init:\n");
DUMPNORTH();
}
diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c
index 5d07441dde..6259608b48 100644
--- a/src/northbridge/intel/i440lx/raminit.c
+++ b/src/northbridge/intel/i440lx/raminit.c
@@ -171,7 +171,7 @@ static void do_ram_command(u32 command)
PRINT_DEBUG_HEX16(reg16);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
read32(addr);
@@ -201,7 +201,7 @@ static void spd_enable_refresh(void)
PRINT_DEBUG("spd_enable_refresh: dramc = 0x");
PRINT_DEBUG_HEX8(reg);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
}
/*-----------------------------------------------------------------------------
@@ -225,7 +225,7 @@ static void northbridge_init(void)
reg32 = pci_read_config32(NB, APBASE);
PRINT_DEBUG("APBASE ");
PRINT_DEBUG_HEX32(reg32);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
}
@@ -244,10 +244,10 @@ static void sdram_set_registers(void)
#if 0
uint16_t reg16;
reg16 = pci_read_config16(NB, PACCFG);
- printk(BIOS_DEBUG, "i82443LX Host Freq: 6%C MHz\r\n", (reg16 & 0x4000) ? '0' : '6');
+ printk(BIOS_DEBUG, "i82443LX Host Freq: 6%C MHz\n", (reg16 & 0x4000) ? '0' : '6');
#endif
- PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge prior to SDRAM init:\n");
DUMPNORTH();
northbridge_init();
@@ -279,11 +279,11 @@ static void sdram_set_registers(void)
} else {
PRINT_DEBUG(" FAIL ");
}
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
}
- PRINT_DEBUG("Northbridge atexit sdram set registers\r\n");
+ PRINT_DEBUG("Northbridge atexit sdram set registers\n");
DUMPNORTH();
}
@@ -342,7 +342,7 @@ static void sdram_set_spd_registers(void)
*/
PRINT_DEBUG_HEX16(ds);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
memsize += ds;
@@ -363,7 +363,7 @@ static void sdram_set_spd_registers(void)
PRINT_DEBUG(" ");
PRINT_DEBUG_HEX16(ds);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/*
* modify DRT register if current row isn't empty
@@ -384,7 +384,7 @@ static void sdram_set_spd_registers(void)
#if 0
PRINT_DEBUG("Mem: 0x");
PRINT_DEBUG_HEX16(memsize * 8);
- PRINT_DEBUG(" MB\r\n");
+ PRINT_DEBUG(" MB\n");
if (memsize == 0) {
/* maybe we should use some nice die/hlt sequence with printing on console
@@ -392,8 +392,8 @@ static void sdram_set_spd_registers(void)
* maybe such event_handler can be commonly defined routine to decrease
* code duplication?
*/
- PRINT_DEBUG("No memory detected via SPD\r\n");
- PRINT_DEBUG("Reverting to hardcoded 64M single side dimm in first bank\r\n");
+ PRINT_DEBUG("No memory detected via SPD\n");
+ PRINT_DEBUG("Reverting to hardcoded 64M single side dimm in first bank\n");
}
#endif
@@ -418,38 +418,38 @@ static void sdram_enable(void)
udelay(200);
/* 1. Apply NOP. Wait 200 clock cycles (clock might be 60 or 66 Mhz). */
- PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
+ PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
do_ram_command(RAM_COMMAND_NOP);
udelay(200);
/* 2. Precharge all. Wait tRP. */
- PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
+ PRINT_DEBUG("RAM Enable 2: Precharge all\n");
do_ram_command(RAM_COMMAND_PRECHARGE);
udelay(1);
/* 3. Perform 8 refresh cycles. Wait tRC each time. */
- PRINT_DEBUG("RAM Enable 3: CBR\r\n");
+ PRINT_DEBUG("RAM Enable 3: CBR\n");
for (i = 0; i < 8; i++) {
do_ram_command(RAM_COMMAND_CBR);
udelay(1);
}
/* 4. Mode register set. Wait two memory cycles. */
- PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
+ PRINT_DEBUG("RAM Enable 4: Mode register set\n");
do_ram_command(RAM_COMMAND_MRS);
udelay(2);
/* 5. Normal operation. */
- PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
+ PRINT_DEBUG("RAM Enable 5: Normal operation\n");
do_ram_command(RAM_COMMAND_NORMAL);
udelay(1);
/* 6. Finally enable refresh. */
- PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n");
+ PRINT_DEBUG("RAM Enable 6: Enable refresh\n");
pci_write_config8(NB, DRAMC, 0x01);
spd_enable_refresh();
udelay(1);
- PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge following SDRAM init:\n");
}
diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c
index 5733700af3..87b039f5f5 100644
--- a/src/northbridge/intel/i82810/debug.c
+++ b/src/northbridge/intel/i82810/debug.c
@@ -2,7 +2,7 @@
static void dump_spd_registers(void)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < DIMM_SOCKETS; i++) {
unsigned device;
device = DIMM_SPD_BASE + i;
@@ -16,20 +16,20 @@ static void dump_spd_registers(void)
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index e88580c5e8..86602eae34 100644
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -150,7 +150,7 @@ static void do_ram_command(u8 command)
PRINT_DEBUG_HEX8(reg8);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
read32(addr);
@@ -164,7 +164,7 @@ static void do_ram_command(u8 command)
PRINT_DEBUG_HEX8(reg8);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(addr);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
#endif
read32(addr);
}
@@ -194,14 +194,14 @@ static void spd_set_dram_size(void)
if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) {
print_debug("Found DIMM in slot ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31);
/* WISHLIST: would be nice to display it as decimal? */
print_debug("DIMM is 0x");
print_debug_hex8(dimm_size * 4);
- print_debug("MB\r\n");
+ print_debug("MB\n");
/* The i810 can't handle DIMMs larger than 128MB per
* side. This will fail if the DIMM uses a
@@ -211,9 +211,9 @@ static void spd_set_dram_size(void)
*/
if (dimm_size > 32) {
print_err("DIMM row sizes larger than 128MB not"
- "supported on i810\r\n");
+ "supported on i810\n");
print_err
- ("Attempting to treat as 128MB DIMM\r\n");
+ ("Attempting to treat as 128MB DIMM\n");
dimm_size = 32;
}
@@ -225,19 +225,19 @@ static void spd_set_dram_size(void)
print_debug("After translation, dimm_size is 0x");
print_debug_hex8(dimm_size);
- print_debug("\r\n");
+ print_debug("\n");
/* If the DIMM is dual-sided, the DRP value is +2 */
/* TODO: Figure out asymetrical configurations. */
if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) ==
0xff) {
- print_debug("DIMM is dual-sided\r\n");
+ print_debug("DIMM is dual-sided\n");
dimm_size += 2;
}
} else {
print_debug("No DIMM found in slot ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
/* If there's no DIMM in the slot, set value to 0. */
dimm_size = 0x00;
@@ -249,7 +249,7 @@ static void spd_set_dram_size(void)
print_debug("DRP calculated to 0x");
print_debug_hex8(drp);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config8(PCI_DEV(0, 0, 0), DRP, drp);
}
@@ -354,7 +354,7 @@ static void set_dram_buffer_strength(void)
print_debug("BUFF_SC calculated to 0x");
print_debug_hex16(buff_sc);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, buff_sc);
}
@@ -411,32 +411,32 @@ static void sdram_enable(void)
int i;
/* 1. Apply NOP. */
- PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
+ PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
do_ram_command(RAM_COMMAND_NOP);
udelay(200);
/* 2. Precharge all. Wait tRP. */
- PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
+ PRINT_DEBUG("RAM Enable 2: Precharge all\n");
do_ram_command(RAM_COMMAND_PRECHARGE);
udelay(1);
/* 3. Perform 8 refresh cycles. Wait tRC each time. */
- PRINT_DEBUG("RAM Enable 3: CBR\r\n");
+ PRINT_DEBUG("RAM Enable 3: CBR\n");
for (i = 0; i < 8; i++) {
do_ram_command(RAM_COMMAND_CBR);
udelay(1);
}
/* 4. Mode register set. Wait two memory cycles. */
- PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
+ PRINT_DEBUG("RAM Enable 4: Mode register set\n");
do_ram_command(RAM_COMMAND_MRS);
udelay(2);
/* 5. Normal operation (enables refresh at 15.6usec). */
- PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
+ PRINT_DEBUG("RAM Enable 5: Normal operation\n");
do_ram_command(RAM_COMMAND_NORMAL);
udelay(1);
- PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge following SDRAM init:\n");
DUMPNORTH();
}
diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c
index f97eaa893d..c9cbdbb8ec 100644
--- a/src/northbridge/intel/i82830/raminit.c
+++ b/src/northbridge/intel/i82830/raminit.c
@@ -79,7 +79,7 @@ static void do_ram_command(u32 command)
pci_write_config32(NORTHBRIDGE, DRC, reg32);
PRINT_DEBUG("RAM command 0x");
PRINT_DEBUG_HEX32(reg32);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
}
static void ram_read32(u8 dimm_start, u32 offset)
@@ -89,24 +89,24 @@ static void ram_read32(u8 dimm_start, u32 offset)
PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024);
PRINT_DEBUG(" => 0x");
PRINT_DEBUG_HEX32(read32(dimm_start * 32 * 1024 * 1024));
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
PRINT_DEBUG(" Writing RAM at 0x");
PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024);
PRINT_DEBUG(" <= 0x");
PRINT_DEBUG_HEX32(offset);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
write32(dimm_start * 32 * 1024 * 1024, offset);
PRINT_DEBUG(" Reading RAM at 0x");
PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024);
PRINT_DEBUG(" => 0x");
PRINT_DEBUG_HEX32(read32(dimm_start * 32 * 1024 * 1024));
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
} else {
PRINT_DEBUG(" Sending RAM command to 0x");
PRINT_DEBUG_HEX32((dimm_start * 32 * 1024 * 1024) + offset);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
read32((dimm_start * 32 * 1024 * 1024) + offset);
}
}
@@ -141,7 +141,7 @@ static void initialize_dimm_rows(void)
if (dimm_end > dimm_start) {
print_debug("Initializing SDRAM Row ");
print_debug_hex8(row);
- print_debug("\r\n");
+ print_debug("\n");
/* NOP command */
PRINT_DEBUG(" NOP ");
@@ -177,7 +177,7 @@ static void initialize_dimm_rows(void)
udelay(1);
/* Perform a dummy memory read/write cycle */
- PRINT_DEBUG(" Performing dummy read/write\r\n");
+ PRINT_DEBUG(" Performing dummy read/write\n");
ram_read32(dimm_start, 0x55aa55aa);
udelay(1);
}
@@ -256,29 +256,29 @@ static void set_dram_row_boundaries(void)
if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
print_debug("Found DIMM in slot ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
sz = spd_get_dimm_size(device);
/* WISHLIST: would be nice to display it as decimal? */
print_debug("DIMM is 0x");
print_debug_hex16(sz.side1);
- print_debug(" on side 1\r\n");
+ print_debug(" on side 1\n");
print_debug("DIMM is 0x");
print_debug_hex16(sz.side2);
- print_debug(" on side 2\r\n");
+ print_debug(" on side 2\n");
/* - Memory compatibility checks - */
/* Test for PC133 (i82830 only supports PC133) */
/* PC133 SPD9 - cycle time is always 75 */
if (spd_read_byte(device, SPD_MIN_CYCLE_TIME_AT_CAS_MAX) != 0x75) {
- print_err("SPD9 DIMM Is Not PC133 Compatable\r\n");
- die("HALT\r\n");
+ print_err("SPD9 DIMM Is Not PC133 Compatable\n");
+ die("HALT\n");
}
/* PC133 SPD10 - access time is always 54 */
if (spd_read_byte(device, SPD_ACCESS_TIME_FROM_CLOCK) != 0x54) {
- print_err("SPD10 DIMM Is Not PC133 Compatable\r\n");
- die("HALT\r\n");
+ print_err("SPD10 DIMM Is Not PC133 Compatable\n");
+ die("HALT\n");
}
/* The i82830 only supports a symmetrical dual-sided dimms
@@ -286,23 +286,23 @@ static void set_dram_row_boundaries(void)
* side or larger than 256MB per side.
*/
if ((sz.side2 != 0) && (sz.side1 != sz.side2)) {
- print_err("This northbridge only supports\r\n");
- print_err("symmetrical dual-sided DIMMs\r\n");
- print_err("booting as a single-sided DIMM\r\n");
+ print_err("This northbridge only supports\n");
+ print_err("symmetrical dual-sided DIMMs\n");
+ print_err("booting as a single-sided DIMM\n");
sz.side2 = 0;
}
if ((sz.side1 < 32)) {
- print_err("DIMMs smaller than 32MB per side\r\n");
- print_err("are not supported on this northbridge\r\n");
- die("HALT\r\n");
+ print_err("DIMMs smaller than 32MB per side\n");
+ print_err("are not supported on this northbridge\n");
+ die("HALT\n");
}
if ((sz.side1 > 256)) {
print_err
- ("DIMMs larger than 256MB per side\r\n");
+ ("DIMMs larger than 256MB per side\n");
print_err
- ("are not supported on this northbridge\r\n");
- die("HALT\r\n");
+ ("are not supported on this northbridge\n");
+ die("HALT\n");
}
/* - End Memory compatibility checks - */
@@ -316,7 +316,7 @@ static void set_dram_row_boundaries(void)
} else {
PRINT_DEBUG("No DIMM found in slot ");
PRINT_DEBUG_HEX8(i);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/* If there's no DIMM in the slot, set value to 0. */
drb1 = 0;
@@ -330,12 +330,12 @@ static void set_dram_row_boundaries(void)
PRINT_DEBUG_HEX8(DRB);
PRINT_DEBUG(" has been set to 0x");
PRINT_DEBUG_HEX8(drb1);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
PRINT_DEBUG("DRB1 0x");
PRINT_DEBUG_HEX8(DRB + 1);
PRINT_DEBUG(" has been set to 0x");
PRINT_DEBUG_HEX8(drb1 + drb2);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
} else if (i == 1) {
value = pci_read_config8(NORTHBRIDGE, DRB + 1);
pci_write_config8(NORTHBRIDGE, DRB + 2, value + drb1);
@@ -344,12 +344,12 @@ static void set_dram_row_boundaries(void)
PRINT_DEBUG_HEX8(DRB + 2);
PRINT_DEBUG(" has been set to 0x");
PRINT_DEBUG_HEX8(value + drb1);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
PRINT_DEBUG("DRB3 0x");
PRINT_DEBUG_HEX8(DRB + 3);
PRINT_DEBUG(" has been set to 0x");
PRINT_DEBUG_HEX8(value + drb1 + drb2);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
/* We need to set the highest DRB value to 0x64 and 0x65.
* These are supposed to be "Reserved" but memory will
@@ -374,7 +374,7 @@ static void set_dram_row_attributes(void)
if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
print_debug("Found DIMM in slot ");
print_debug_hex8(i);
- print_debug(", setting DRA...\r\n");
+ print_debug(", setting DRA...\n");
dra = 0x00;
@@ -403,8 +403,8 @@ static void set_dram_row_attributes(void)
} else if (dra == 16) {
dra = 0xF3; /* 16KB */
} else {
- print_err("Page size not supported\r\n");
- die("HALT\r\n");
+ print_err("Page size not supported\n");
+ die("HALT\n");
}
} else if (value == 2) {
if (dra == 2) {
@@ -416,18 +416,18 @@ static void set_dram_row_attributes(void)
} else if (dra == 16) {
dra = 0x33; /* 16KB */
} else {
- print_err("Page size not supported\r\n");
- die("HALT\r\n");
+ print_err("Page size not supported\n");
+ die("HALT\n");
}
} else {
- print_err("# of banks of DIMM not supported\r\n");
- die("HALT\r\n");
+ print_err("# of banks of DIMM not supported\n");
+ die("HALT\n");
}
} else {
PRINT_DEBUG("No DIMM found in slot ");
PRINT_DEBUG_HEX8(i);
- PRINT_DEBUG(", setting DRA to 0xFF\r\n");
+ PRINT_DEBUG(", setting DRA to 0xFF\n");
/* If there's no DIMM in the slot, set dra value to 0xFF. */
dra = 0xFF;
@@ -439,7 +439,7 @@ static void set_dram_row_attributes(void)
PRINT_DEBUG_HEX8(DRA + i);
PRINT_DEBUG(" has been set to 0x");
PRINT_DEBUG_HEX8(dra);
- PRINT_DEBUG("\r\n");
+ PRINT_DEBUG("\n");
}
}
@@ -468,7 +468,7 @@ Public interface.
static void sdram_set_registers(void)
{
- PRINT_DEBUG("Setting initial sdram registers....\r\n");
+ PRINT_DEBUG("Setting initial sdram registers....\n");
/* Calculate the value for DRT DRAM Timing Register */
set_dram_timing();
@@ -482,7 +482,7 @@ static void sdram_set_registers(void)
/* Setup DRAM Row Attribute Registers */
set_dram_row_attributes();
- PRINT_DEBUG("Initial sdram registers have been set.\r\n");
+ PRINT_DEBUG("Initial sdram registers have been set.\n");
}
static void northbridge_set_registers(void)
@@ -490,7 +490,7 @@ static void northbridge_set_registers(void)
u16 value;
int igd_memory = 0;
- PRINT_DEBUG("Setting initial nothbridge registers....\r\n");
+ PRINT_DEBUG("Setting initial nothbridge registers....\n");
/* Set the value for Fixed DRAM Hole Control Register */
pci_write_config8(NORTHBRIDGE, FDHC, 0x00);
@@ -536,7 +536,7 @@ static void northbridge_set_registers(void)
value |= 1; // 64MB aperture
pci_write_config16(NORTHBRIDGE, GCC1, value);
- PRINT_DEBUG("Initial northbridge registers have been set.\r\n");
+ PRINT_DEBUG("Initial northbridge registers have been set.\n");
}
static void sdram_initialize(void)
@@ -554,13 +554,13 @@ static void sdram_initialize(void)
initialize_dimm_rows();
/* Enable Refresh */
- PRINT_DEBUG("Enabling Refresh\r\n");
+ PRINT_DEBUG("Enabling Refresh\n");
reg32 = pci_read_config32(NORTHBRIDGE, DRC);
reg32 |= (RAM_COMMAND_REFRESH << 8);
pci_write_config32(NORTHBRIDGE, DRC, reg32);
/* Set initialization complete */
- PRINT_DEBUG("Setting initialization complete\r\n");
+ PRINT_DEBUG("Setting initialization complete\n");
reg32 = pci_read_config32(NORTHBRIDGE, DRC);
reg32 |= (RAM_COMMAND_IC << 29);
pci_write_config32(NORTHBRIDGE, DRC, reg32);
@@ -568,6 +568,6 @@ static void sdram_initialize(void)
/* Setup Initial Northbridge Registers */
northbridge_set_registers();
- PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+ PRINT_DEBUG("Northbridge following SDRAM init:\n");
DUMPNORTH();
}
diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c
index 4083add6f1..40da896589 100644
--- a/src/northbridge/intel/i855/debug.c
+++ b/src/northbridge/intel/i855/debug.c
@@ -60,7 +60,7 @@ static void print_pci_devices(void)
continue;
}
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
}
}
@@ -68,7 +68,7 @@ static void dump_pci_device(unsigned dev)
{
int i;
print_debug_pci_dev(dev);
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i <= 255; i++) {
unsigned char val;
@@ -80,7 +80,7 @@ static void dump_pci_device(unsigned dev)
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
@@ -105,7 +105,7 @@ static void dump_pci_devices(void)
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 0; i < 2; i++) {
unsigned device;
device = ctrl->channel0[i];
@@ -119,20 +119,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
#if 0
device = ctrl->channel1[i];
@@ -146,20 +146,20 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
#endif
}
@@ -167,7 +167,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
static void dump_smbus_registers(void)
{
int i;
- print_debug("\r\n");
+ print_debug("\n");
for(i = 1; i < 0x80; i++) {
unsigned device;
device = i;
@@ -178,20 +178,20 @@ static void dump_smbus_registers(void)
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\r\n");
+ print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\r\n");
+ print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
#endif
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 8e928bd279..136266da2c 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -31,7 +31,7 @@
static void sdram_set_registers(const struct mem_controller *ctrl)
{
/*
- print_debug("Before configuration:\r\n");
+ print_debug("Before configuration:\n");
dump_pci_devices();
*/
}
@@ -212,7 +212,7 @@ static void ram_command_mrs(const struct mem_controller *ctrl,
adjusted_mode = ((mode & 0x800) << (13 - 11)) | ((mode & 0x3ff) << (12 - 9));
print_debug("Setting mode: ");
print_debug_hex32(adjusted_mode + addr);
- print_debug("\r\n");
+ print_debug("\n");
read32(adjusted_mode + addr);
}
@@ -229,39 +229,39 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{
int i;
uint32_t rank1 = (1 << 30) / 2;
- print_debug("Ram enable 1\r\n");
+ print_debug("Ram enable 1\n");
delay();
delay();
- print_debug("Ram enable 2\r\n");
+ print_debug("Ram enable 2\n");
ram_command(ctrl, 1, 0);
ram_command(ctrl, 1, rank1);
delay();
delay();
- print_debug("Ram enable 3\r\n");
+ print_debug("Ram enable 3\n");
ram_command(ctrl, 2, 0);
ram_command(ctrl, 2, rank1);
delay();
delay();
- print_debug("Ram enable 4\r\n");
+ print_debug("Ram enable 4\n");
ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, 0);
ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, rank1);
delay();
delay();
- print_debug("Ram enable 5\r\n");
+ print_debug("Ram enable 5\n");
ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, 0);
ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, rank1);
- print_debug("Ram enable 6\r\n");
+ print_debug("Ram enable 6\n");
ram_command(ctrl, 2, 0);
ram_command(ctrl, 2, rank1);
delay();
delay();
- print_debug("Ram enable 7\r\n");
+ print_debug("Ram enable 7\n");
for(i = 0; i < 8; i++) {
ram_command(ctrl, 6, 0);
ram_command(ctrl, 6, rank1);
@@ -269,28 +269,28 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
delay();
}
- print_debug("Ram enable 8\r\n");
+ print_debug("Ram enable 8\n");
ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_NORMAL, 0);
ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_NORMAL, rank1);
- print_debug("Ram enable 9\r\n");
+ print_debug("Ram enable 9\n");
ram_command(ctrl, 7, 0);
ram_command(ctrl, 7, rank1);
delay();
delay();
- print_debug("Ram enable 9\r\n");
+ print_debug("Ram enable 9\n");
set_initialize_complete(ctrl);
delay();
delay();
delay();
- print_debug("After configuration:\r\n");
+ print_debug("After configuration:\n");
/* dump_pci_devices(); */
/*
- print_debug("\n\n***** RAM TEST *****\r\n");
+ print_debug("\n\n***** RAM TEST *****\n");
ram_check(0, 0xa0000);
ram_check(0x100000, 0x40000000);
*/
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 23:05:29 +0000