summaryrefslogtreecommitdiff
path: root/src/northbridge/intel
diff options
context:
space:
mode:
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/haswell/gma.c4
-rw-r--r--src/northbridge/intel/haswell/northbridge.c12
2 files changed, 11 insertions, 5 deletions
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index f22ff48707..75f3b7a944 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -252,13 +252,13 @@ static void gma_pm_init_pre_vbios(struct device *dev)
gtt_write_regs(haswell_gt_setup);
/* Wait for Mailbox Ready */
- gtt_poll(0x138124, (1 << 31), (0 << 31));
+ gtt_poll(0x138124, (1UL << 31), (0UL << 31));
/* Mailbox Data - RC6 VIDS */
gtt_write(0x138128, 0x00000000);
/* Mailbox Command */
gtt_write(0x138124, 0x80000004);
/* Wait for Mailbox Ready */
- gtt_poll(0x138124, (1 << 31), (0 << 31));
+ gtt_poll(0x138124, (1UL << 31), (0UL << 31));
/* Enable PM Interrupts */
gtt_write(GEN6_PMIER, GEN6_PM_MBOX_EVENT | GEN6_PM_THERMAL_EVENT |
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index a8c8015d97..32be916a45 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -36,6 +36,7 @@
static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
{
u32 pciexbar_reg;
+ u32 mask;
*base = 0;
*len = 0;
@@ -47,15 +48,20 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
switch ((pciexbar_reg >> 1) & 3) {
case 0: // 256MB
- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
+ mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
+ *base = pciexbar_reg & mask;
*len = 256 * 1024 * 1024;
return 1;
case 1: // 128M
- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
+ mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
+ mask |= (1 << 27);
+ *base = pciexbar_reg & mask;
*len = 128 * 1024 * 1024;
return 1;
case 2: // 64M
- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
+ mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
+ mask |= (1 << 27) | (1 << 26);
+ *base = pciexbar_reg & mask;
*len = 64 * 1024 * 1024;
return 1;
}