3 files changed, 6 insertions, 32 deletions
diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c
index 7a5d0b1ce5..4a8696d45a 100644
--- a/src/northbridge/intel/gm45/acpi.c
+++ b/src/northbridge/intel/gm45/acpi.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <types.h>
+#include <commonlib/helpers.h>
 #include <console/console.h>
 #include <acpi/acpi.h>
 #include <acpi/acpigen.h>
@@ -12,40 +13,12 @@
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
-	struct device *dev;
-	u32 pciexbar = 0;
-	u32 pciexbar_reg;
-	int max_buses;
+	u32 length, pciexbar;
 
-	dev = dev_find_device(0x8086, 0x2a40, 0);
-	if (!dev)
+	if (!decode_pcie_bar(&pciexbar, &length))
 		return current;
 
-	pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO);
-
-	// MMCFG not supported or not enabled.
-	if (!(pciexbar_reg & (1 << 0)))
-		return current;
-
-	switch ((pciexbar_reg >> 1) & 3) {
-	case 0: // 256MB
-		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
-		max_buses = 256;
-		break;
-	case 1: // 128M
-		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
-		max_buses = 128;
-		break;
-	case 2: // 64M
-		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
-		max_buses = 64;
-		break;
-	default: // RSVD
-		return current;
-	}
-
-	if (!pciexbar)
-		return current;
+	const int max_buses = length / MiB;
 
 	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
 			pciexbar, 0x0, 0x0, max_buses - 1);
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index d9cfbf7090..d18b3d42c8 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -433,6 +433,7 @@ struct blc_pwm_t {
 int get_blc_values(const struct blc_pwm_t **entries);
 u16 get_blc_pwm_freq_value(const char *edid_ascii_string);
 
+int decode_pcie_bar(u32 *const base, u32 *const len);
 
 #include <device/device.h>
 
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index e58ed0d967..8c27d50eb6 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -21,7 +21,7 @@
 static const int legacy_hole_base_k = 0xa0000 / 1024;
 static const int legacy_hole_size_k = 128;
 
-static int decode_pcie_bar(u32 *const base, u32 *const len)
+int decode_pcie_bar(u32 *const base, u32 *const len)
 {
 	*base = 0;
 	*len = 0;