diff options
Diffstat (limited to 'src/northbridge/intel')
64 files changed, 64 insertions, 0 deletions
diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c index c21e321de4..357a9633b6 100644 --- a/src/northbridge/intel/e7505/debug.c +++ b/src/northbridge/intel/e7505/debug.c @@ -15,6 +15,7 @@ #include <console/console.h> #include <stdlib.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <spd.h> #include "raminit.h" diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index 1b86012907..afe11bbe01 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -15,6 +15,7 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> +#include <device/pci_ops.h> #include <arch/cpu.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 317f0874f8..0032356697 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -13,6 +13,7 @@ #include <console/console.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <stdint.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 70a0d66950..276307dfa5 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -27,6 +27,7 @@ #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <lib.h> #include <stdlib.h> #include <commonlib/helpers.h> diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 25560dd0e3..ca439a0d9a 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <arch/acpi.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <stdint.h> #include <delay.h> #include <cpu/intel/fsp_model_406dx/model_406dx.h> diff --git a/src/northbridge/intel/fsp_rangeley/port_access.c b/src/northbridge/intel/fsp_rangeley/port_access.c index 91e017993c..c93d3bd029 100644 --- a/src/northbridge/intel/fsp_rangeley/port_access.c +++ b/src/northbridge/intel/fsp_rangeley/port_access.c @@ -18,6 +18,7 @@ #include <stdint.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> #include "northbridge.h" diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index dc5937230f..301743ce4a 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -21,6 +21,7 @@ #include <arch/acpigen.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_ops.h> #include "gm45.h" unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index 8a61e1c9be..5b1c301cfd 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -12,6 +12,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> /* Just re-define these instead of including gm45.h. It blows up romcc. */ #define D0F0_PCIEXBAR_LO 0x60 diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index c2e4aea2ac..723a43f6bf 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -15,6 +15,7 @@ #include <stdint.h> #include <arch/io.h> +#include <device/pci_ops.h> #include "gm45.h" void gm45_early_init(void) diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index c987cb3e2c..9f919cfbcd 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -16,6 +16,7 @@ #include <types.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <halt.h> #include "gm45.h" diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index 45144aae2e..b0e2ba9916 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -17,6 +17,7 @@ #include <stdint.h> #include <stddef.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> #include <pc80/mc146818rtc.h> diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index f42456413b..642c8776ef 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -18,6 +18,7 @@ #include <string.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <device/pci_def.h> #include <arch/acpi.h> diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 791559b518..fddb1fe339 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -16,6 +16,7 @@ #include <cbmem.h> #include <console/console.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <stdint.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 5d6c182550..1a6e3de1da 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -18,6 +18,7 @@ #include <stddef.h> #include <string.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index af1a46dd67..c1ef30e684 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <arch/cpu.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> #include <cpu/intel/romstage.h> diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 176c16a5d7..d4209dc51f 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -18,6 +18,7 @@ #include <stdlib.h> #include <arch/cpu.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <device/pci_def.h> #include <device/device.h> #include <spd.h> diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index 6d652bb8d8..7335ac914f 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -19,6 +19,7 @@ #include <romstage_handoff.h> #include <console/console.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <arch/acpi.h> #include <cpu/x86/lapic.h> #include <cpu/x86/bist.h> diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index f655c3b6fb..d92e858d53 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -20,6 +20,7 @@ #include <arch/acpi.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_ops.h> #include "haswell.h" #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index a25f363177..d7f4e6e9e9 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -12,6 +12,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> /* Just re-define this instead of including haswell.h. It blows up romcc. */ #define PCIEXBAR 0x60 diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index be83894f33..a04b3f4720 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -14,6 +14,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> #include <bootmode.h> diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c index d3e88f2f84..24fbb64b97 100644 --- a/src/northbridge/intel/haswell/ram_calc.c +++ b/src/northbridge/intel/haswell/ram_calc.c @@ -17,6 +17,7 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> +#include <device/pci_ops.h> #include <cbmem.h> #include "haswell.h" diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 1bc31108f5..376e63f7d5 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -18,6 +18,7 @@ #include <string.h> #include <southbridge/intel/lynxpoint/pch.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <cpu/x86/msr.h> #include "haswell.h" diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c index cff3ade0f5..b4d92b0d51 100644 --- a/src/northbridge/intel/i440bx/debug.c +++ b/src/northbridge/intel/i440bx/debug.c @@ -13,6 +13,7 @@ #include <console/console.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <spd.h> #include "raminit.h" diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 4b1141c7ff..ae897662c0 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -13,6 +13,7 @@ #include <console/console.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <stdint.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c index 962f3ba6f6..3207688b4d 100644 --- a/src/northbridge/intel/i440bx/ram_calc.c +++ b/src/northbridge/intel/i440bx/ram_calc.c @@ -16,6 +16,7 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> +#include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> #include <commonlib/helpers.h> diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 49994edf17..0c9496b2d5 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <stdlib.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> #include "i440bx.h" diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index 053815bbfd..f817cdf570 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -20,6 +20,7 @@ #include <arch/acpigen.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_ops.h> #include "i945.h" unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 5296d52e40..1c00e8bebf 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -12,6 +12,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> /* Just re-define this instead of including i945.h. It blows up romcc. */ #define PCIEXBAR 0x48 diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index c52f2a67e8..370131fb51 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -16,6 +16,7 @@ #include <spd.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> #include "i945.h" diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index b82812e6d1..d9d88bb445 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <arch/acpi.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <device/pci_def.h> #include <cbmem.h> #include <halt.h> diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 7a2a489c6b..3a01940e64 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -18,6 +18,7 @@ #include <delay.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_ops.h> #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> #include <edid.h> diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 7c209dc32f..1dff3d14dd 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -16,6 +16,7 @@ #include <cbmem.h> #include <console/console.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <stdint.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index fd37aea08c..c797d42f09 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -17,6 +17,7 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> +#include <device/pci_ops.h> #include <arch/cpu.h> #include <cbmem.h> #include "i945.h" diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index dece9bffae..c6a2e05b3b 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -17,6 +17,7 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <device/pci_def.h> +#include <device/pci_ops.h> #include <device/device.h> #include <lib.h> #include <pc80/mc146818rtc.h> diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index 08fc09c534..462cdc07fa 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -21,6 +21,7 @@ #include <types.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_ops.h> #include "nehalem.h" unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/nehalem/bootblock.c index 807e91936f..c37aa3a61d 100644 --- a/src/northbridge/intel/nehalem/bootblock.c +++ b/src/northbridge/intel/nehalem/bootblock.c @@ -12,6 +12,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> static void bootblock_northbridge_init(void) { diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index ac0ed45d4c..2c958a4c86 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -19,6 +19,7 @@ #include <stdlib.h> #include <console/console.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <device/pci_def.h> #include <elog.h> #include <cpu/x86/msr.h> diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index fbe6c11546..43ec6ed6bd 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <arch/acpi.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <stdint.h> #include <delay.h> #include <cpu/intel/model_2065x/model_2065x.h> diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index baf087e412..3df6f8153f 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -18,6 +18,7 @@ #include <arch/cpu.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> #include <cpu/intel/romstage.h> diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index c730b5ef5f..9812e532e4 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <string.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <cpu/x86/msr.h> #include <cbmem.h> #include <arch/cbfs.h> diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/nehalem/smi.c index a08ac1b02e..6aefc9b141 100644 --- a/src/northbridge/intel/nehalem/smi.c +++ b/src/northbridge/intel/nehalem/smi.c @@ -17,6 +17,7 @@ #include <string.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_ops.h> #include "nehalem.h" #include <cpu/intel/smm/gen1/smi.h> diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index 1fab845db2..f3eab492f5 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -12,6 +12,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> #define PCIEXBAR 0x60 #define MMCONF_256_BUSSES 16 #define ENABLE 1 diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 89744289a2..11dc203d1e 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -18,6 +18,7 @@ #include <stdlib.h> #include <console/console.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <device/pci_def.h> #include <device/pci.h> #include <halt.h> diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index ec2c902b90..94aed89fc2 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -17,6 +17,7 @@ #include <cbmem.h> #include <console/console.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <stdint.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index 21b926bc9a..cf9db988e1 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -17,6 +17,7 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> +#include <device/pci_ops.h> #include <device/device.h> #include <device/pci_def.h> #include <console/console.h> diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index ed633fd745..1b2ad8de6f 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -15,6 +15,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <delay.h> diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 10ac0f53b4..0d2cc368da 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -20,6 +20,7 @@ #include <lib.h> #include <timestamp.h> #include <console/console.h> +#include <device/pci_ops.h> #include <cbmem.h> #include <romstage_handoff.h> #include <southbridge/intel/i82801gx/i82801gx.h> diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index c2743189fb..4afb54646d 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -21,6 +21,7 @@ #include <arch/acpi.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_ops.h> #include "sandybridge.h" #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 05b0c7558c..c35a49a51b 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -12,6 +12,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> /* Just re-define this instead of including sandybridge.h. It blows up romcc. */ #define PCIEXBAR 0x60 diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index f8ecc1a77a..01787f13a9 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -18,6 +18,7 @@ #include <stdlib.h> #include <console/console.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <arch/acpi.h> #include <device/pci_def.h> #include <elog.h> diff --git a/src/northbridge/intel/sandybridge/iommu.c b/src/northbridge/intel/sandybridge/iommu.c index 017c73233c..26bbdf995b 100644 --- a/src/northbridge/intel/sandybridge/iommu.c +++ b/src/northbridge/intel/sandybridge/iommu.c @@ -17,6 +17,7 @@ #include <stdint.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <device/device.h> #include <device/pci_def.h> diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 0d644ca14a..4d00d738cd 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -17,6 +17,7 @@ #include <console/console.h> #include <arch/acpi.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <stdint.h> #include <delay.h> #include <cpu/intel/model_206ax/model_206ax.h> diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index bb88c7a02e..53fb4d3530 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -17,6 +17,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_ops.h> #include <device/pciexp.h> #include <device/pci_ids.h> #include <assert.h> diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c index 00e3e785a7..0e5127de94 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -17,6 +17,7 @@ #include <arch/cpu.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> #include <cpu/intel/romstage.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 5f7fd0a8ca..115d515517 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -21,6 +21,7 @@ #include <string.h> #include <arch/cpu.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <cbmem.h> #include <halt.h> #include <timestamp.h> diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 489758135d..afdd9084c4 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -19,6 +19,7 @@ #include <string.h> #include <arch/cpu.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <northbridge/intel/sandybridge/chip.h> #include <device/pci_def.h> #include <delay.h> diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index af9b490554..6142388c5b 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -18,6 +18,7 @@ #include <bootmode.h> #include <string.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 26f49772f8..c979897354 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -19,6 +19,7 @@ #include <string.h> #include <console/console.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <cpu/x86/lapic.h> #include <timestamp.h> #include "sandybridge.h" diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 9629d887c2..b470e955e1 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -15,6 +15,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> #include "iomap.h" #include "x4x.h" diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index c6eb38315b..9cb3df3565 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -16,6 +16,7 @@ #include <stdint.h> #include <arch/io.h> +#include <device/pci_ops.h> #include "iomap.h" #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/i82801gx.h> /* DEFAULT_PMBASE */ diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 4b5a754a1c..c168e38f51 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -17,6 +17,7 @@ #include <cbmem.h> #include <console/console.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <stdint.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 6484326e57..ff3c31b4f5 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -22,6 +22,7 @@ #include <stdint.h> #include <arch/cpu.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> #include <cpu/intel/romstage.h> diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 1fd600484f..ea00f293e1 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -15,6 +15,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> #include <cpu/x86/cache.h> diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 5c5dafa644..ffa861eb66 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -17,6 +17,7 @@ #include <assert.h> #include <stdint.h> #include <arch/io.h> +#include <device/pci_ops.h> #include <console/console.h> #include <commonlib/helpers.h> #include <delay.h> |