diff options
Diffstat (limited to 'src/northbridge/intel')
30 files changed, 81 insertions, 81 deletions
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index fcf347c54f..3bb1f67b59 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -54,7 +54,7 @@ Definitions: // Unfortunately the code seems to chew up several K of space. //#define VALIDATE_DIMM_COMPATIBILITY -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) #define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x) #define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x) #define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x) diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index 79775757b5..ec36c06c16 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -97,7 +97,7 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) if (config->MrcRmtCpgcNumBursts) { UpdData->PcdMrcRmtCpgcNumBursts = config->MrcRmtCpgcNumBursts; } -#if IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT) +#if CONFIG(ENABLE_FSP_FAST_BOOT) UpdData->PcdFastboot = UPD_ENABLE; #endif /* diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 4a5ebbd0a0..648aa48fef 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -190,7 +190,7 @@ static void gma_func0_init(struct device *dev) mmio = res2mmio(gtt_res, 0, 0); - if (!IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) { /* PCI Init, will run VBIOS */ printk(BIOS_DEBUG, "Initialising IGD using VBIOS\n"); pci_dev_init(dev); @@ -205,7 +205,7 @@ static void gma_func0_init(struct device *dev) /* Post VBIOS init */ gma_pm_init_post_vbios(dev, edid_lvds.ascii_string); - if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; if (vga_disable) { printk(BIOS_INFO, diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index e9d35207c7..0f0d38339e 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -33,7 +33,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) +#if CONFIG(CHROMEOS_RAMOOPS) Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) #endif diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 3b043a3b96..0fd0228268 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -35,7 +35,7 @@ #include "chip.h" #include "haswell.h" -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #endif @@ -240,7 +240,7 @@ static void power_well_enable(void) * after we power up the AUX channel until we can talk to it. * So get that going right now. We can't turn on the panel, yet, just VDD. */ - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { gtt_write(PCH_PP_CONTROL, PCH_PP_UNLOCK| EDP_FORCE_VDD | PANEL_POWER_RESET); } } @@ -475,7 +475,7 @@ static void gma_func0_init(struct device *dev) int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; - if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (vga_disable) { printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index ac0b84f1d0..ad4563bb35 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -395,7 +395,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) +#if CONFIG(CHROMEOS_RAMOOPS) reserved_ram_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index bf88418203..91959c7cd8 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -31,7 +31,7 @@ */ /* Debugging macros. */ -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) #define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x) #define DUMPNORTH() dump_pci_device(NB) #else @@ -297,7 +297,7 @@ static const u8 register_values[] = { * 0 = 3 clocks of RAS# precharge * 1 = 2 clocks of RAS# precharge */ -#if IS_ENABLED(CONFIG_SDRAMPWR_4DIMM) +#if CONFIG(SDRAMPWR_4DIMM) SDRAMC + 0, 0x00, 0x10, /* The board has 4 DIMM slots. */ #else SDRAMC + 0, 0x00, 0x00, /* The board has 3 DIMM slots. */ @@ -460,7 +460,7 @@ static void set_dram_buffer_strength(void) } } - if (IS_ENABLED(CONFIG_SDRAMPWR_4DIMM)) { + if (CONFIG(SDRAMPWR_4DIMM)) { /* * For a 4 DIMM board, based on ASUS P2B-LS mainboard. * diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index e20d559fa4..4711359181 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -29,7 +29,7 @@ void sdram_enable(void); void sdram_initialize(void); /* Debug */ -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) void dump_spd_registers(void); void dump_pci_device(unsigned dev); #else diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 1913b524a5..7ab252585a 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -93,7 +93,7 @@ static void i945m_detect_chipset(void) } printk(BIOS_DEBUG, "\n"); - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); } @@ -143,7 +143,7 @@ static void i945_detect_chipset(void) } printk(BIOS_DEBUG, "\n"); - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); } @@ -237,7 +237,7 @@ static void i945_setup_egress_port(void) /* Egress Port Virtual Channel 1 Configuration */ reg32 = EPBAR32(0x2c); reg32 &= 0xffffff00; - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { if ((MCHBAR32(CLKCFG) & 7) == 0) reg32 |= 0x1a; /* 1067MHz */ } @@ -256,7 +256,7 @@ static void i945_setup_egress_port(void) reg32 |= (0x0a << 16); EPBAR32(EPVC1RCAP) = reg32; - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { if ((MCHBAR32(CLKCFG) & 7) == 0) { /* 1067MHz */ EPBAR32(EPVC1IST + 0) = 0x01380138; EPBAR32(EPVC1IST + 4) = 0x01380138; @@ -941,14 +941,14 @@ void i945_late_initialization(int s3resume) i945_setup_dmi_rcrb(); - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) i945_setup_pci_express_x16(); i945_setup_root_complex_topology(); -#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if !CONFIG(HAVE_ACPI_RESUME) #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) sdram_dump_mchbar_registers(); { diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 26b6c84352..633b09d31b 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -236,9 +236,9 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / (pixel_n + 2) / (pixel_p1 * pixel_p2)); - printk(BIOS_INFO, "VGA mode: %s\n", IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER) ? + printk(BIOS_INFO, "VGA mode: %s\n", CONFIG(LINEAR_FRAMEBUFFER) ? "Linear framebuffer" : "text"); - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { + if (CONFIG(LINEAR_FRAMEBUFFER)) { /* Disable panel fitter (we're in native resolution). */ write32(mmiobase + PF_CTL(0), 0); write32(mmiobase + PF_WIN_SZ(0), 0); @@ -301,7 +301,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) | (vactive + bottom_border + vfront_porch - 1)); - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { + if (CONFIG(LINEAR_FRAMEBUFFER)) { write32(mmiobase + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1)); } else { @@ -380,7 +380,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, else printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { + if (CONFIG(LINEAR_FRAMEBUFFER)) { printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", (void *)pgfx, hactive * vactive * 4); memset((void *)pgfx, 0x00, hactive * vactive * 4); @@ -660,7 +660,7 @@ static void gma_ngi(struct device *const dev) int err; - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) panel_setup(mmiobase, dev); /* probe if VGA is connected and always run */ @@ -704,7 +704,7 @@ static void gma_func0_init(struct device *dev) int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { if (acpi_is_wakeup_s3()) { printk(BIOS_INFO, "Skipping native VGA initialization when resuming from ACPI S3.\n"); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a9bfde7805..a93cf1e718 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -33,7 +33,7 @@ #include <timestamp.h> /* Debugging macros. */ -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) #else #define PRINTK_DEBUG(x...) @@ -96,7 +96,7 @@ static void ram_read32(u32 offset) read32((void *)offset); } -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) void sdram_dump_mchbar_registers(void) { int i; @@ -112,7 +112,7 @@ void sdram_dump_mchbar_registers(void) static int memclk(void) { - int offset = IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; + int offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { case 1: return 400; @@ -127,7 +127,7 @@ static int memclk(void) static u16 fsbclk(void) { - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { switch (MCHBAR32(CLKCFG) & 7) { case 0: return 400; case 1: return 533; @@ -137,7 +137,7 @@ static u16 fsbclk(void) MCHBAR32(CLKCFG) & 7); } return 0xffff; - } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { switch (MCHBAR32(CLKCFG) & 7) { case 0: return 1066; case 1: return 533; @@ -386,7 +386,7 @@ static void gather_common_timing(struct sys_info *sysinfo, bytes_read = i2c_eeprom_read(device, 0, 64, raw_spd); printk(BIOS_DEBUG, "Reading SPD using i2c block operation.\n"); - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) && bytes_read > 0) + if (CONFIG(DEBUG_RAM_SETUP) && bytes_read > 0) hexdump(raw_spd, bytes_read); if (bytes_read != 64) { /* Try again with SMBUS byte read */ @@ -394,7 +394,7 @@ static void gather_common_timing(struct sys_info *sysinfo, " trying smbus byte operation.\n"); for (j = 0; j < 64; j++) raw_spd[j] = spd_read_byte(device, j); - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) + if (CONFIG(DEBUG_RAM_SETUP)) hexdump(raw_spd, 64); } @@ -404,7 +404,7 @@ static void gather_common_timing(struct sys_info *sysinfo, continue; } - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) + if (CONFIG(DEBUG_RAM_SETUP)) dram_print_spd_ddr2(&dimm_info); if (dimm_info.flags.is_ecc) @@ -841,7 +841,7 @@ static const u32 *slew_group_lookup(int dual_channel, int index) return nc; } -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) +#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) /* Strength multiplier tables */ static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, @@ -896,7 +896,7 @@ static const u8 single_channel_strength_multiplier[] = { 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 }; -#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) +#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, @@ -1027,7 +1027,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0); /* We drive both channels with the same speed */ - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { switch (sysinfo->memory_frequency) { case 400: channeldll = 0x26262626; break; @@ -1036,7 +1036,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) case 667: channeldll = 0x11111111; break; } - } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { switch (sysinfo->memory_frequency) { case 400: channeldll = 0x33333333; break; @@ -1052,7 +1052,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = channeldll; MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = channeldll; MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = channeldll; - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; } @@ -1769,7 +1769,7 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo) { u32 clkcfg; u8 reg8; - u8 offset = IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; + u8 offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; printk(BIOS_DEBUG, "Setting Memory Frequency... "); @@ -1854,7 +1854,7 @@ static void sdram_program_clock_crossing(void) /** * We add the indices according to our clocks from CLKCFG. */ -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) +#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) static const u32 data_clock_crossing[] = { 0x00100401, 0x00000000, /* DDR400 FSB400 */ 0xffffffff, 0xffffffff, /* nonexistent */ @@ -1899,7 +1899,7 @@ static void sdram_program_clock_crossing(void) 0xffffffff, 0xffffffff, /* nonexistent */ }; -#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) +#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) /* i945 G/P */ static const u32 data_clock_crossing[] = { 0xffffffff, 0xffffffff, /* nonexistent */ @@ -2119,7 +2119,7 @@ static void sdram_post_jedec_initialization(struct sys_info *sysinfo) if (sysinfo->interleaved) { reg32 = MCHBAR32(DCC); -#if IS_ENABLED(CONFIG_CHANNEL_XOR_RANDOMIZATION) +#if CONFIG(CHANNEL_XOR_RANDOMIZATION) reg32 &= ~(1 << 10); reg32 |= (1 << 9); #else @@ -2175,7 +2175,7 @@ static void sdram_power_management(struct sys_info *sysinfo) reg32 |= (1 << 12) | (1 << 11); MCHBAR32(C1DRC1) = reg32; - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { if (i945_silicon_revision() > 1) { /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ u16 peg_bits = (1 << 5) | (1 << 0); @@ -2493,9 +2493,9 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo) { u8 clocks[2] = { 0, 0 }; -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) +#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) #define CLOCKS_WIDTH 2 -#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) +#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) #define CLOCKS_WIDTH 3 #endif if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) @@ -2510,7 +2510,7 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo) if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH; -#if IS_ENABLED(CONFIG_OVERRIDE_CLOCK_DISABLE) +#if CONFIG(OVERRIDE_CLOCK_DISABLE) /* Usually system firmware turns off system memory clock signals * to unused SO-DIMM slots to reduce EMI and power consumption. * However, the Kontron 986LCD-M does not like unused clock @@ -2755,7 +2755,7 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) * Program Graphics Frequency * Set core display and render clock on 945GC to the max */ - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) sdram_program_graphics_frequency(&sysinfo); else pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 98bdc02afd..2d1eee6947 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -70,7 +70,7 @@ void sdram_initialize(int boot_path, const u8 *sdram_addresses); int fixup_i945_errata(void); void udelay(u32 us); -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) void sdram_dump_mchbar_registers(void); #endif #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/nehalem/acpi/nehalem.asl index 664022bf0f..df8aad7c62 100644 --- a/src/northbridge/intel/nehalem/acpi/nehalem.asl +++ b/src/northbridge/intel/nehalem/acpi/nehalem.asl @@ -33,7 +33,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) +#if CONFIG(CHROMEOS_RAMOOPS) Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) #endif diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 2c958a4c86..a5cac7b19a 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -73,7 +73,7 @@ static void nehalem_setup_bars(void) pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33); pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33); -#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) +#if CONFIG(ELOG_BOOT_COUNT) /* Increment Boot Counter for non-S3 resume */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) @@ -82,7 +82,7 @@ static void nehalem_setup_bars(void) printk(BIOS_DEBUG, " done.\n"); -#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) +#if CONFIG(ELOG_BOOT_COUNT) /* Increment Boot Counter except when resuming from S3 */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index be17e2fa12..86fc583f88 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -603,7 +603,7 @@ static void gma_func0_init(struct device *dev) /* Init graphics power management */ gma_pm_init_pre_vbios(dev); - if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { struct northbridge_intel_nehalem_config *conf = dev->chip_info; int lightup_ok; printk(BIOS_SPEW, "Initializing VGA without OPROM."); diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 6906714457..8a4f64c809 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -78,7 +78,7 @@ static void add_fixed_resources(struct device *dev, int index) reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) +#if CONFIG(CHROMEOS_RAMOOPS) reserved_ram_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); @@ -90,7 +90,7 @@ static void pci_domain_set_resources(struct device *dev) assign_resources(dev->link_list); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static const char *northbridge_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -114,7 +114,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = northbridge_acpi_name, #endif }; diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 73a82407fe..8bacc77598 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -268,7 +268,7 @@ static void gma_func0_init(struct device *dev) reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { /* PCI Init, will run VBIOS */ pci_dev_init(dev); } else { diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 4cdb27a898..5aea59ef17 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -28,7 +28,7 @@ #include <string.h> /* Debugging macros. */ -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) #else #define PRINTK_DEBUG(x...) @@ -134,7 +134,7 @@ static int decode_spd(struct dimminfo *d, int i) d->tRCD = d->spd_data[29]; d->tWR = d->spd_data[36]; d->ranks = d->sides; // XXX -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) const char *ubso[2] = { "UB", "SO" }; #endif PRINTK_DEBUG("%s-DIMM %d\n", &ubso[d->type][0], i); @@ -311,7 +311,7 @@ static void sdram_read_spds(struct sysinfo *s) } } -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) static u32 fsb_reg_to_mhz(u32 speed) { return (speed * 133) + 667; diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 73692037c3..dce9f67029 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -35,7 +35,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) +#if CONFIG(CHROMEOS_RAMOOPS) Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) #endif diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 44eebf3215..ad579c6fc3 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -59,7 +59,7 @@ static void sandybridge_setup_bars(void) pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); -#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) +#if CONFIG(ELOG_BOOT_COUNT) /* Increment Boot Counter for non-S3 resume */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) @@ -68,7 +68,7 @@ static void sandybridge_setup_bars(void) printk(BIOS_DEBUG, " done.\n"); -#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) +#if CONFIG(ELOG_BOOT_COUNT) /* Increment Boot Counter except when resuming from S3 */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) @@ -159,7 +159,7 @@ static void start_peg_link_training(void) * As the MRC has its own initialization code skip it. */ if (((pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID) & BASE_REV_MASK) != BASE_REV_IVB) || - IS_ENABLED(CONFIG_HAVE_MRC)) + CONFIG(HAVE_MRC)) return; deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index ce2abd9d88..00180fe4f0 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -625,7 +625,7 @@ static void gma_func0_init(struct device *dev) /* Init graphics power management */ gma_pm_init_pre_vbios(dev); - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) /* PCI Init, will run VBIOS */ pci_dev_init(dev); @@ -636,7 +636,7 @@ static void gma_func0_init(struct device *dev) /* Running graphics init on S3 breaks Linux drm driver. */ if (!acpi_is_wakeup_s3() && - IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (vga_disable) { printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index ab0554c7df..e58a0ebc3a 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -98,7 +98,7 @@ static void add_fixed_resources(struct device *dev, int index) reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); -#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) +#if CONFIG(CHROMEOS_RAMOOPS) reserved_ram_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index 53fb4d3530..16bc314b90 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -28,7 +28,7 @@ static void pcie_disable(struct device *dev) dev->enabled = 0; } -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) static const char *pcie_acpi_name(const struct device *dev) { assert(dev); @@ -90,7 +90,7 @@ static struct device_operations device_ops = { .disable = pcie_disable, .init = pci_dev_init, .ops_pci = &pci_ops, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) .acpi_name = pcie_acpi_name, #endif }; diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index caba76efac..3f62d10a1c 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -210,7 +210,7 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) printram("XMP profile supports %u DIMMs, but %u DIMMs are installed.\n", dimm->dimm[channel][slot].dimms_per_channel, dimms_on_channel); - if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS)) + if (CONFIG(NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS)) printk(BIOS_WARNING, "XMP maximum DIMMs will be ignored.\n"); else spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 6bda9ed3dd..fda662f4f6 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -390,7 +390,7 @@ unsigned int get_mem_min_tck(void) /* If this is zero, it just means devicetree.cb didn't set it */ if (!cfg || cfg->max_mem_clock_mhz == 0) { - if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) + if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) return TCK_1333MHZ; rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 853fdb83d0..852da7aa26 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -41,7 +41,7 @@ * MRC scrambler seed offsets should be reserved in * mainboard cmos.layout and not covered by checksum. */ -#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) +#if CONFIG(USE_OPTION_TABLE) #include "option_table.h" #define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3) #define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3) @@ -241,7 +241,7 @@ void sdram_initialize(struct pei_data *pei_data) } /* mrc.bin reconfigures USB, so reinit it to have debug */ - if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) + if (CONFIG(USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); /* For reference print the System Agent version diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 9cb3df3565..5ccc77e9be 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -18,7 +18,7 @@ #include <arch/io.h> #include <device/pci_ops.h> #include "iomap.h" -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/i82801gx.h> /* DEFAULT_PMBASE */ #else #include <southbridge/intel/i82801jx/i82801jx.h> /* DEFAULT_PMBASE */ diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 7e91cc5f5d..8de568a0ea 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -36,9 +36,9 @@ #include <pc80/vga.h> #include <pc80/vga_io.h> -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX) +#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) #include <southbridge/intel/i82801jx/nvs.h> -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/nvs.h> #endif @@ -71,7 +71,7 @@ static void gma_func0_init(struct device *dev) int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; - if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (vga_disable) { printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index ea00f293e1..72ef1a915e 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -25,7 +25,7 @@ #include <halt.h> #include <lib.h> #include "iomap.h" -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */ #else #include <southbridge/intel/i82801jx/i82801jx.h> /* smbus_read_byte */ @@ -174,7 +174,7 @@ static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd, return CB_ERR; } - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) + if (CONFIG(DEBUG_RAM_SETUP)) dram_print_spd_ddr2(&decoded_dimm); if (!(decoded_dimm.width & (0x08 | 0x10))) { @@ -383,7 +383,7 @@ static int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd, if (spd_decode_ddr3(&decoded_dimm, raw_spd) != SPD_STATUS_OK) return CB_ERR; - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) + if (CONFIG(DEBUG_RAM_SETUP)) dram_print_spd_ddr3(&decoded_dimm); /* x4 DIMMs are not supported (true for both ddr2 and ddr3) */ diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index d14809e827..f172623108 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -21,7 +21,7 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <delay.h> -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/i82801gx.h> #else #include <southbridge/intel/i82801jx/i82801jx.h> |