diff options
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/raminit.c | 6 |
2 files changed, 2 insertions, 8 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 9f027343e4..ac61ca47ee 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -535,14 +535,14 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -void *cbmem_top(void) +unsigned long get_top_of_ram(void) { u32 reg; /* The top the reserve regions fall just below the TSEG region. */ reg = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG); - return (void *)(reg & ~((1 << 20) - 1)); + return (reg & ~((1 << 20) - 1)); } static void northbridge_enable(device_t dev) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index c1095a7eb7..a90b360116 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -202,12 +202,6 @@ void sdram_initialize(struct pei_data *pei_data) report_memory_config(); } -void *cbmem_top(void) -{ - /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ - return (void *)get_top_of_ram(); -} - unsigned long get_top_of_ram(void) { /* |