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path: root/src/northbridge/intel/x4x/raminit_tables.c
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Diffstat (limited to 'src/northbridge/intel/x4x/raminit_tables.c')
-rw-r--r--src/northbridge/intel/x4x/raminit_tables.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c
index 8ff93c9230..401af15cd8 100644
--- a/src/northbridge/intel/x4x/raminit_tables.c
+++ b/src/northbridge/intel/x4x/raminit_tables.c
@@ -289,6 +289,23 @@ const u8 ddr3_emrs1_rtt_nom_config[16][4] = { /* [Config][Rank] */
{0x81, 0x00, 0x81, 0x00}, /* 16S_16S */
};
+const u8 post_jedec_tab[3][4][2]= /* [FSB][DDR freq][17:13 or 12:8] */
+{ /* FSB DDR */
+ {{0x3, 0x5}, /* 800 667 */
+ {0x3, 0x4}, /* 800 800 */
+ },
+ {{0x4, 0x8}, /* 1067 667 */
+ {0x4, 0x6}, /* 1067 800 */
+ {0x3, 0x5}, /* 1067 1066 */
+ },
+ {{0x5, 0x9}, /* 1333 667 */
+ {0x4, 0x7}, /* 1333 800 */
+ {0x4, 0x7}, /* 1333 1066 */
+ {0x4, 0x7} /* 1333 1333 */
+ },
+};
+
+
const u32 ddr3_c2_tab[2][3][6][2] = { /* [n-mode][ddr3 freq][CAS][reg] */
/* 115h[15:0] 117h[23:0] */
{ /* 1N mode */