aboutsummaryrefslogtreecommitdiff
path: root/src/northbridge/intel/x4x/ram_calc.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/northbridge/intel/x4x/ram_calc.c')
-rw-r--r--src/northbridge/intel/x4x/ram_calc.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index d5743e3733..49afdc3b69 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -105,9 +105,10 @@ void *cbmem_top(void)
#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-/* setup_stack_and_mtrrs() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use. */
-void *setup_stack_and_mtrrs(void)
+/* platform_enter_postcar() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use,
+ * and continues execution in postcar stage. */
+void platform_enter_postcar(void)
{
struct postcar_frame pcf;
uintptr_t top_of_ram;
@@ -130,8 +131,7 @@ void *setup_stack_and_mtrrs(void)
postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
- /* Save the number of MTRRs to setup. Return the stack location
- * pointing to the number of MTRRs.
- */
- return postcar_commit_mtrrs(&pcf);
+ run_postcar_phase(&pcf);
+
+ /* We do not return here. */
}