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path: root/src/northbridge/intel/x4x/early_init.c
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Diffstat (limited to 'src/northbridge/intel/x4x/early_init.c')
-rw-r--r--src/northbridge/intel/x4x/early_init.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index 279a38fcd6..ea41e76dce 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -15,13 +15,13 @@
void x4x_early_init(void)
{
/* Setup MCHBAR. */
- pci_write_config32(HOST_BRIDGE, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1);
+ pci_write_config32(HOST_BRIDGE, D0F0_MCHBAR_LO, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
/* Setup DMIBAR. */
- pci_write_config32(HOST_BRIDGE, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1);
+ pci_write_config32(HOST_BRIDGE, D0F0_DMIBAR_LO, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
/* Setup EPBAR. */
- pci_write_config32(HOST_BRIDGE, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
+ pci_write_config32(HOST_BRIDGE, D0F0_EPBAR_LO, CONFIG_FIXED_EPBAR_MMIO_BASE | 1);
/* Setup HECIBAR */
pci_write_config32(PCI_DEV(0, 3, 0), 0x10, DEFAULT_HECIBAR);