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-rw-r--r--src/northbridge/intel/sch/chip.h22
-rw-r--r--src/northbridge/intel/sch/northbridge.c1
2 files changed, 0 insertions, 23 deletions
diff --git a/src/northbridge/intel/sch/chip.h b/src/northbridge/intel/sch/chip.h
deleted file mode 100644
index b3aebd35c8..0000000000
--- a/src/northbridge/intel/sch/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-struct northbridge_intel_sch_config {
-};
-
diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c
index 48556e2f92..16ada2fa6c 100644
--- a/src/northbridge/intel/sch/northbridge.c
+++ b/src/northbridge/intel/sch/northbridge.c
@@ -29,7 +29,6 @@
#include <bitops.h>
#include <cpu/cpu.h>
#include <arch/acpi.h>
-#include "chip.h"
#include "sch.h"
static int get_pcie_bar(u32 *base, u32 *len)