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-rw-r--r--src/northbridge/intel/sandybridge/raminit.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 2b46873e4d..b5a1c23f94 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -205,6 +205,13 @@ static void report_memory_config(void)
}
}
+static void post_system_agent_init(struct pei_data *pei_data)
+{
+ /* If PCIe init is skipped, set the PEG clock gating */
+ if (!pei_data->pcie_init)
+ MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01;
+}
+
/**
* Find PEI executable in coreboot filesystem and execute it.
*
@@ -289,6 +296,7 @@ void sdram_initialize(struct pei_data *pei_data)
else
intel_early_me_status();
+ post_system_agent_init(pei_data);
report_memory_config();
/* S3 resume: don't save scrambler seed or MRC data */