diff options
Diffstat (limited to 'src/northbridge/intel/sandybridge/sandybridge.h')
| -rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 53fb3eb9b0..ef1df061d6 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -132,6 +132,7 @@ enum platform_type { #define Ly(r, y) ((r) + ((y) * 4)) #define Cx(r, x) ((r) + ((x) * 0x400)) #define CxLy(r, x, y) ((r) + ((x) * 0x400) + ((y) * 4)) +#define GzLy(r, z, y) ((r) + ((z) * 0x100) + ((y) * 4)) /* byte lane training register base addresses */ #define LANEBASE_B0 0x0000 @@ -144,6 +145,13 @@ enum platform_type { #define LANEBASE_B7 0x1600 #define LANEBASE_ECC 0x0800 /* ECC lane is in the middle of the data lanes */ +/* byte lane register offsets */ +#define GDCRTRAININGRESULT(ch, y) GzLy(0x0004, ch, y) /* Test results for PI config */ +#define GDCRTRAININGRESULT1(ch) GDCRTRAININGRESULT(ch, 0) /* 0x0004 */ +#define GDCRTRAININGRESULT2(ch) GDCRTRAININGRESULT(ch, 1) /* 0x0008 */ +#define GDCRRX(ch, rank) GzLy(0x10, ch, rank) /* Time setting for lane Rx */ +#define GDCRTX(ch, rank) GzLy(0x20, ch, rank) /* Time setting for lane Tx */ + /* Register definitions */ #define GDCRCLKRANKSUSED_ch(ch) Gz(0x0c00, ch) /* Indicates which rank is populated */ #define GDCRCLKCOMP_ch(ch) Gz(0x0c04, ch) /* RCOMP result register */ |