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Diffstat (limited to 'src/northbridge/intel/sandybridge/romstage.c')
-rw-r--r--src/northbridge/intel/sandybridge/romstage.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index fad8e2f91a..49f334e397 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -5,7 +5,6 @@
#include <device/pci_ops.h>
#include <cpu/x86/lapic.h>
#include <romstage_handoff.h>
-#include <timestamp.h>
#include "sandybridge.h"
#include <arch/romstage.h>
#include <device/pci_def.h>
@@ -63,8 +62,6 @@ void mainboard_romstage_entry(void)
perform_raminit(s3resume);
- timestamp_add_now(TS_AFTER_INITRAM);
-
post_code(0x3b);
/* Perform some initialization that must run before stage2 */
early_pch_reset_pmcon();