diff options
Diffstat (limited to 'src/northbridge/intel/sandybridge/romstage.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 81049e55c4..ec44ee2c8a 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -39,20 +39,18 @@ static void early_pch_reset_pmcon(void) { u8 reg8; - // reset rtc power status + /* Reset RTC power status */ reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); reg8 &= ~(1 << 2); pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); } -/* Platform has no romstage entry point under mainboard directory, - * so this one is named with prefix mainboard. - */ +/* The romstage entry point for this platform is not mainboard-specific, hence the name */ void mainboard_romstage_entry(void) { int s3resume = 0; - if (MCHBAR16(SSKPD) == 0xCAFE) + if (MCHBAR16(SSKPD_HI) == 0xCAFE) system_reset(); enable_lapic(); @@ -60,14 +58,12 @@ void mainboard_romstage_entry(void) /* Init LPC, GPIO, BARs, disable watchdog ... */ early_pch_init(); - /* USB is initialized in MRC if MRC is used. */ + /* When using MRC, USB is initialized by MRC */ if (CONFIG(USE_NATIVE_RAMINIT)) { early_usb_init(mainboard_usb_ports); } - /* Perform some early chipset initialization required - * before RAM initialization can work - */ + /* Perform some early chipset init needed before RAM initialization can work */ systemagent_early_init(); printk(BIOS_DEBUG, "Back from systemagent_early_init()\n"); |