aboutsummaryrefslogtreecommitdiff
path: root/src/northbridge/intel/sandybridge/romstage.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/northbridge/intel/sandybridge/romstage.c')
-rw-r--r--src/northbridge/intel/sandybridge/romstage.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 5c0dd5c1a7..fad8e2f91a 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -4,6 +4,7 @@
#include <cf9_reset.h>
#include <device/pci_ops.h>
#include <cpu/x86/lapic.h>
+#include <romstage_handoff.h>
#include <timestamp.h>
#include "sandybridge.h"
#include <arch/romstage.h>
@@ -75,7 +76,9 @@ void mainboard_romstage_entry(void)
post_code(0x3d);
- northbridge_romstage_finalize(s3resume);
+ northbridge_romstage_finalize();
post_code(0x3f);
+
+ romstage_handoff_init(s3resume);
}