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Diffstat (limited to 'src/northbridge/intel/sandybridge/romstage.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 34d759f419..3d05f8e3fa 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -103,6 +103,9 @@ void main(unsigned long bist) s3resume = southbridge_detect_s3_resume(); post_code(0x38); + + mainboard_early_init(s3resume); + /* Enable SPD ROMs and DDR-III DRAM */ enable_smbus(); |