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path: root/src/northbridge/intel/sandybridge/raminit_mrc.c
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Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_mrc.c')
-rw-r--r--src/northbridge/intel/sandybridge/raminit_mrc.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 053a4873cd..1f6b75c95f 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -199,13 +199,6 @@ static void report_memory_config(void)
}
}
-static void post_system_agent_init(struct pei_data *pei_data)
-{
- /* If PCIe init is skipped, set the PEG clock gating */
- if (!pei_data->pcie_init)
- MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01;
-}
-
/**
* Find PEI executable in coreboot filesystem and execute it.
*
@@ -288,6 +281,5 @@ void sdram_initialize(struct pei_data *pei_data)
else
intel_early_me_status();
- post_system_agent_init(pei_data);
report_memory_config();
}