diff options
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_common.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 25 |
1 files changed, 11 insertions, 14 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 702addaf92..c69c827136 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1155,8 +1155,7 @@ void program_timings(ramctr_timing *ctrl, int channel) shift_402x) << (8 * slotrank); FOR_ALL_LANES { - MCHBAR32(lane_base[lane] + - (0x10 + (channel * 0x100) + (slotrank * 4))) = + MCHBAR32(lane_base[lane] + GDCRRX(channel, slotrank)) = (((ctrl->timings[channel][slotrank].lanes[lane]. timA + shift) & 0x3f) | @@ -1169,8 +1168,7 @@ void program_timings(ramctr_timing *ctrl, int channel) | ((ctrl->timings[channel][slotrank].lanes[lane]. falling + shift) << 20)); - MCHBAR32(lane_base[lane] + - (0x20 + (channel * 0x100) + (slotrank * 4))) = + MCHBAR32(lane_base[lane] + GDCRTX(channel, slotrank)) = (((ctrl->timings[channel][slotrank].lanes[lane]. timC + shift) & 0x3f) | @@ -1230,8 +1228,8 @@ static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, int lane) { u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; - return ((MCHBAR32(lane_base[lane] + (4 + (channel * 0x100) + - (((timA / 32) & 1) * 4))) >> (timA % 32)) & 1); + return ((MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT(channel, (timA / 32) & 1)) >> + (timA % 32)) & 1); } struct run { @@ -1891,10 +1889,9 @@ static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) test_timB(ctrl, channel, slotrank); FOR_ALL_LANES { - statistics[lane][timB] = - !((MCHBAR32(lane_base[lane] + (4 + - (channel * 0x100) + (((timB / 32) & 1) * 4))) - >> (timB % 32)) & 1); + statistics[lane][timB] = !((MCHBAR32(lane_base[lane] + + GDCRTRAININGRESULT(channel, (timB / 32) & 1)) >> + (timB % 32)) & 1); } } FOR_ALL_LANES { @@ -2015,9 +2012,9 @@ static void adjust_high_timB(ramctr_timing *ctrl) wait_for_iosav(channel); FOR_ALL_LANES { - u64 res = MCHBAR32(lane_base[lane] + 4 + (channel * 0x100) + (0 * 4)); + u64 res = MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT1(channel)); res |= ((u64) MCHBAR32(lane_base[lane] + - (4 + (channel * 0x100) + (1 * 4)))) << 32; + GDCRTRAININGRESULT2(channel))) << 32; old = ctrl->timings[channel][slotrank].lanes[lane].timB; ctrl->timings[channel][slotrank].lanes[lane].timB += get_timB_high_adjust(res) * 64; @@ -3023,9 +3020,9 @@ void write_controller_mr(ramctr_timing *ctrl) int channel, slotrank; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - MCHBAR32(lane_base[slotrank] + (0x0004 + (channel * 0x100) + (0 * 4))) = + MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT1(channel)) = make_mr0(ctrl, slotrank); - MCHBAR32(lane_base[slotrank] + (0x0004 + (channel * 0x100) + (1 * 4))) = + MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT2(channel)) = make_mr1(ctrl, slotrank, channel); } } |