diff options
Diffstat (limited to 'src/northbridge/intel/sandybridge/northbridge.c')
-rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5ff123e63b..a9b1c251d0 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -391,15 +391,15 @@ static void northbridge_init(struct device *dev) northbridge_dmi_init(dev); - bridge_type = MCHBAR32(0x5f10); + bridge_type = MCHBAR32(SAPMTIMERS); bridge_type &= ~0xff; if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { /* Enable Power Aware Interrupt Routing */ - u8 pair = MCHBAR8(0x5418); + u8 pair = MCHBAR8(PAIR_CTL); pair &= ~0xf; /* Clear 3:0 */ pair |= 0x4; /* Fixed Priority */ - MCHBAR8(0x5418) = pair; + MCHBAR8(PAIR_CTL) = pair; /* 30h for IvyBridge */ bridge_type |= 0x30; @@ -407,7 +407,7 @@ static void northbridge_init(struct device *dev) /* 20h for Sandybridge */ bridge_type |= 0x20; } - MCHBAR32(0x5f10) = bridge_type; + MCHBAR32(SAPMTIMERS) = bridge_type; /* Turn off unused devices. Has to be done before * setting BIOS_RESET_CPL. @@ -433,12 +433,12 @@ static void northbridge_init(struct device *dev) */ if (cpu_config_tdp_levels()) { msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT); - MCHBAR32(0x59A0) = msr.lo; - MCHBAR32(0x59A4) = msr.hi; + MCHBAR32(MC_TURBO_PL1) = msr.lo; + MCHBAR32(MC_TURBO_PL2) = msr.hi; } /* Set here before graphics PM init */ - MCHBAR32(0x5500) = 0x00100001; + MCHBAR32(MMIO_PAVP_CTL) = 0x00100001; } void northbridge_write_smram(u8 smram) |