diff options
Diffstat (limited to 'src/northbridge/intel/sandybridge/gma.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/gma.c | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index f75dfda616..86e12b0c64 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -4,6 +4,7 @@ #include <device/mmio.h> #include <console/console.h> #include <bootmode.h> +#include <cpu/intel/model_206ax/model_206ax.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> @@ -301,6 +302,8 @@ int gtt_poll(u32 reg, u32 mask, u32 value) static void gma_pm_init_pre_vbios(struct device *dev) { + const bool is_sandy = is_sandybridge(); + u32 reg32; printk(BIOS_DEBUG, "GT Power Management Init\n"); @@ -309,7 +312,7 @@ static void gma_pm_init_pre_vbios(struct device *dev) if (!gtt_res || !gtt_res->base) return; - if (bridge_silicon_revision() < IVB_STEP_C0) { + if (is_sandy || cpu_stepping() < IVB_STEP_C0) { /* 1: Enable force wake */ gtt_write(0xa18c, 0x00000001); gtt_poll(0x130090, (1 << 0), (1 << 0)); @@ -319,14 +322,14 @@ static void gma_pm_init_pre_vbios(struct device *dev) gtt_poll(0x130040, (1 << 0), (1 << 0)); } - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + if (is_sandy) { /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ reg32 = gtt_read(0x42004); reg32 |= (1 << 14) | (1 << 15); gtt_write(0x42004, reg32); } - if (bridge_silicon_revision() >= IVB_STEP_A0) { + if (!is_sandy) { /* Display Reset Acknowledge Settings */ reg32 = gtt_read(0x45010); reg32 |= (1 << 1) | (1 << 0); @@ -335,7 +338,7 @@ static void gma_pm_init_pre_vbios(struct device *dev) /* 2: Get GT SKU from GTT+0x911c[13] */ reg32 = gtt_read(0x911c); - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + if (is_sandy) { if (reg32 & (1 << 13)) { printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n"); gtt_write_powermeter(snb_pm_gt1); @@ -384,13 +387,12 @@ static void gma_pm_init_pre_vbios(struct device *dev) reg32 = gtt_read(0xa180); reg32 |= (1 << 26) | (1 << 31); /* (bit 20=1 for SNB step D1+ / IVB A0+) */ - if (bridge_silicon_revision() >= SNB_STEP_D1) + if (!is_sandy || cpu_stepping() >= SNB_STEP_D1) reg32 |= (1 << 20); gtt_write(0xa180, reg32); /* 6a: for SnB step D2+ only */ - if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && - (bridge_silicon_revision() >= SNB_STEP_D2)) { + if (is_sandy && cpu_stepping() >= SNB_STEP_D2) { reg32 = gtt_read(0x9400); reg32 |= (1 << 7); gtt_write(0x9400, reg32); @@ -402,16 +404,16 @@ static void gma_pm_init_pre_vbios(struct device *dev) gtt_poll(0x941c, (1 << 1), (0 << 1)); } - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + if (is_sandy) { + /* 6b: Clocking reset controls */ + gtt_write(0x9424, 0x00000000); + } else { reg32 = gtt_read(0x907c); reg32 |= (1 << 16); gtt_write(0x907c, reg32); /* 6b: Clocking reset controls */ gtt_write(0x9424, 0x00000001); - } else { - /* 6b: Clocking reset controls */ - gtt_write(0x9424, 0x00000000); } /* 7 */ @@ -503,7 +505,7 @@ static void gma_pm_init_post_vbios(struct device *dev) printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); /* 15: Deassert Force Wake */ - if (bridge_silicon_revision() < IVB_STEP_C0) { + if (is_sandybridge() || cpu_stepping() < IVB_STEP_C0) { gtt_write(0xa18c, gtt_read(0xa18c) & ~1); gtt_poll(0x130090, (1 << 0), (0 << 0)); } else { |