diff options
Diffstat (limited to 'src/northbridge/intel/sandybridge/gma.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/gma.c | 16 |
1 files changed, 2 insertions, 14 deletions
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 4a043ebb35..b9a07a2d72 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -622,25 +622,12 @@ static void gma_pm_init_post_vbios(struct device *dev) static void gma_func0_init(struct device *dev) { u32 reg32; - u32 graphics_base, graphics_size; /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); - /* Set up an MTRR for the graphics memory BAR to vastly improve - * speed of VGA initialization (and later access). To stay out of - * the way of the MTRR init code, we are using MTRR #8 to cover - * that range. - */ - graphics_base = dev->resource_list[1].base; - graphics_size = dev->resource_list[1].size; - printk(BIOS_DEBUG, "Setting up MTRR for graphics 0x%08x (%dK)\n", - graphics_base, graphics_size / 1024); - set_var_mtrr(8, graphics_base >> 10, graphics_size >> 10, - MTRR_TYPE_WRCOMB, 0x24); - /* Init graphics power management */ gma_pm_init_pre_vbios(dev); @@ -655,10 +642,11 @@ static void gma_func0_init(struct device *dev) #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); - u32 iobase, mmiobase, physbase; + u32 iobase, mmiobase, physbase, graphics_base; iobase = dev->resource_list[2].base; mmiobase = dev->resource_list[0].base; physbase = pci_read_config32(dev, 0x5c) & ~0xf; + graphics_base = dev->resource_list[1].base; int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); i915lightup(physbase, iobase, mmiobase, graphics_base); |