3 files changed, 83 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
index 5988489243..09b8892141 100644
--- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
@@ -37,7 +37,8 @@ Device (MCHC)
 		MHEN,	 1,	// Enable
 		,	13,	//
 		MHBR,	22,	// MCHBAR
-
+		Offset (0x54),
+		DVEN,	32,
 		Offset (0x60),	// PCIe BAR
 		PXEN,	 1,	// Enable
 		PXSZ,	 2,	// BAR size
diff --git a/src/northbridge/intel/sandybridge/acpi/peg.asl b/src/northbridge/intel/sandybridge/acpi/peg.asl
new file mode 100644
index 0000000000..f98a4ce083
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/acpi/peg.asl
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017-2018 Patrick Rudolph <siro@das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Device (PEGP)
+{
+	Name (_ADR, 0x00010000)
+
+	Method (_STA)
+	{
+		ShiftRight (\_SB.PCI0.MCHC.DVEN, 3, Local0)
+		Return (And (Local0, 1))
+	}
+
+	Device (DEV0)
+	{
+		Name(_ADR, 0x00000000)
+	}
+}
+
+Device (PEG1)
+{
+	Name (_ADR, 0x00010001)
+
+	Method (_STA)
+	{
+		ShiftRight (\_SB.PCI0.MCHC.DVEN, 2, Local0)
+		Return (And (Local0, 1))
+	}
+
+	Device (DEV0)
+	{
+		Name(_ADR, 0x00000000)
+	}
+}
+
+Device (PEG2)
+{
+	Name (_ADR, 0x00010002)
+
+	Method (_STA)
+	{
+		ShiftRight (\_SB.PCI0.MCHC.DVEN, 1, Local0)
+		Return (And (Local0, 1))
+	}
+
+	Device (DEV0)
+	{
+		Name(_ADR, 0x00000000)
+	}
+}
+
+Device (PEG6)
+{
+	Name (_ADR, 0x00060000)
+
+	Method (_STA)
+	{
+		ShiftRight (\_SB.PCI0.MCHC.DVEN, 13, Local0)
+		Return (And (Local0, 1))
+	}
+
+	Device (DEV0)
+	{
+		Name(_ADR, 0x00000000)
+	}
+}
diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
index 609106f082..3076a68a9a 100644
--- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2017-2018 Patrick Rudolph <siro@das-labor.org>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -16,6 +17,7 @@
 
 #include "../sandybridge.h"
 #include "hostbridge.asl"
+#include "peg.asl"
 
 /* PCI Device Resource Consumption */
 Device (PDRC)