diff options
Diffstat (limited to 'src/northbridge/intel/pineview')
| -rw-r--r-- | src/northbridge/intel/pineview/memmap.c | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 9908f110cd..b4fef6bc76 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -24,9 +24,9 @@ #include <cbmem.h> #include <northbridge/intel/pineview/pineview.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <cpu/intel/smm_reloc.h> #include <stdint.h> -#include <stage_cache.h> u8 decode_pciebar(u32 *const base, u32 *const len) { @@ -116,13 +116,13 @@ static u32 decode_tseg_size(const u32 esmramc) } } -u32 northbridge_get_tseg_size(void) +static size_t northbridge_get_tseg_size(void) { const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); return decode_tseg_size(esmramc); } -u32 northbridge_get_tseg_base(void) +static uintptr_t northbridge_get_tseg_base(void) { return pci_read_config32(PCI_DEV(0, 0, 0), TSEG); } @@ -139,14 +139,10 @@ void *cbmem_top(void) } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - /* The stage cache lives at the end of the TSEG region. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() - + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); + *start = northbridge_get_tseg_base(); + *size = northbridge_get_tseg_size(); } void fill_postcar_frame(struct postcar_frame *pcf) |