diff options
Diffstat (limited to 'src/northbridge/intel/pineview')
| -rw-r--r-- | src/northbridge/intel/pineview/memmap.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/raminit.c | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 146fff2136..bebe3a5b69 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -106,7 +106,6 @@ static uintptr_t northbridge_get_tseg_base(void) return pci_read_config32(HOST_BRIDGE, TSEG); } - /* * Depending of UMA and TSEG configuration, TSEG might start at any 1 MiB alignment. * As this may cause very greedy MTRR setup, push CBMEM top downwards to 4 MiB boundary. diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 43149be723..2248d03c89 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -941,7 +941,6 @@ static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk) MCHBAR8_AND_OR(C0TXDQS0R0DLL + j, ~0x3f, reg8); } - static void sdram_p_dq(struct pllparam *pll, u8 f, u8 clk) { u8 rank, dq, reg8, j; |