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path: root/src/northbridge/intel/pineview/romstage.c
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Diffstat (limited to 'src/northbridge/intel/pineview/romstage.c')
-rw-r--r--src/northbridge/intel/pineview/romstage.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c
index 41fb0f6720..8d7de45149 100644
--- a/src/northbridge/intel/pineview/romstage.c
+++ b/src/northbridge/intel/pineview/romstage.c
@@ -57,20 +57,12 @@ void mainboard_romstage_entry(unsigned long bist)
if (bist == 0)
enable_lapic();
- /* Disable watchdog timer */
- RCBA32(GCS) = RCBA32(GCS) | 0x20;
-
/* Enable GPIOs */
pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
- mb_enable_lpc(); // nm10_enable_lpc
-
- /* Initialize console device(s) */
- console_init();
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);