diff options
Diffstat (limited to 'src/northbridge/intel/pineview/ram_calc.c')
| -rw-r--r-- | src/northbridge/intel/pineview/ram_calc.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index d1b43aa42d..a3caaf713a 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -26,6 +26,8 @@ #include <cpu/x86/mtrr.h> #include <cpu/intel/romstage.h> #include <cpu/intel/smm/gen1/smi.h> +#include <stdint.h> +#include <stage_cache.h> u8 decode_pciebar(u32 *const base, u32 *const len) { @@ -138,6 +140,17 @@ void *cbmem_top(void) } +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)(northbridge_get_tseg_base() + + CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ |