diff options
Diffstat (limited to 'src/northbridge/intel/nehalem/northbridge.c')
-rw-r--r-- | src/northbridge/intel/nehalem/northbridge.c | 48 |
1 files changed, 0 insertions, 48 deletions
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 4ab89ad054..7b9283fb90 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -226,55 +226,7 @@ static void northbridge_dmi_init(struct device *dev) static void northbridge_init(struct device *dev) { - u8 bios_reset_cpl; - u32 bridge_type; - northbridge_dmi_init(dev); - - bridge_type = MCHBAR32(0x5f10); - bridge_type &= ~0xff; - - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { - /* Enable Power Aware Interrupt Routing */ - u8 pair = MCHBAR8(0x5418); - pair &= ~0xf; /* Clear 3:0 */ - pair |= 0x4; /* Fixed Priority */ - MCHBAR8(0x5418) = pair; - - /* 30h for IvyBridge */ - bridge_type |= 0x30; - } else { - /* 20h for Sandybridge */ - bridge_type |= 0x20; - } - MCHBAR32(0x5f10) = bridge_type; - - /* - * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU - * that BIOS has initialized memory and power management - */ - bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); - bios_reset_cpl |= 1; - MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; - printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); - - /* Configure turbo power limits 1ms after reset complete bit */ - mdelay(1); -#ifdef DISABLED - set_power_limits(28); - - /* - * CPUs with configurable TDP also need power limits set - * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. - */ - if (cpu_config_tdp_levels()) { - msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT); - MCHBAR32(0x59A0) = msr.lo; - MCHBAR32(0x59A4) = msr.hi; - } -#endif - /* Set here before graphics PM init */ - MCHBAR32(0x5500) = 0x00100001; } static struct pci_operations intel_pci_ops = { |