diff options
Diffstat (limited to 'src/northbridge/intel/ironlake/romstage.c')
| -rw-r--r-- | src/northbridge/intel/ironlake/romstage.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index 6b9f3d0e83..8d3cfd6811 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -24,7 +24,6 @@ */ void mainboard_romstage_entry(void) { - u32 reg32; int s3resume = 0; u8 spd_addrmap[4] = {}; @@ -60,14 +59,5 @@ void mainboard_romstage_entry(void) intel_early_me_status(); - if (s3resume) { - /* - * Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } - romstage_handoff_init(s3resume); } |